CWE-1298 Base Draft

Hardware Logic Contains Race Conditions

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.

Definition

What is CWE-1298?

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.
In hardware design, race conditions happen when signals from the same source take different paths through logic gates and arrive at slightly different times. This timing mismatch can cause a gate's output to flicker into an incorrect state—a glitch—before settling correctly. These glitches, though often brief, create a window where the hardware operates in an unintended state. When these timing errors occur in security-sensitive circuits like access control modules or cryptographic state machines, they become critical vulnerabilities. Attackers can deliberately trigger or amplify these glitches to bypass authentication, escalate privileges, or leak protected data, effectively undermining the hardware's security guarantees.
Auswirkungen in der Praxis

Real-world CVEs caused by CWE-1298

Bisher sind in MITREs Katalog keine öffentlichen CVE-Referenzen mit dieser CWE verknüpft.

Wie Angreifer es ausnutzen

Angreiferpfad Schritt für Schritt

  1. 1

    The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.

  2. 2

    The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.

  3. 3

    This line of code removes the glitch in signal z.

  4. 4

    The example code is taken from the DMA (Direct Memory Access) module of the buggy OpenPiton SoC of HACK@DAC'21. The DMA contains a finite-state machine (FSM) for accessing the permissions using the physical memory protection (PMP) unit. PMP provides secure regions of physical memory against unauthorized access. It allows an operating system or a hypervisor to define a series of physical memory regions and then set permissions for those regions, such as read, write, and execute permissions. When a user tries to access a protected memory area (e.g., through DMA), PMP checks the access of a PMP address (e.g., pmpaddr_i) against its configuration (pmpcfg_i). If the access violates the defined permissions (e.g., CTRL_ABORT), the PMP can trigger a fault or an interrupt. This access check is implemented in the pmp parametrized module in the below code snippet. The below code assumes that the state of the pmpaddr_i and pmpcfg_i signals will not change during the different DMA states (i.e., CTRL_IDLE to CTRL_DONE) while processing a DMA request (via dma_ctrl_reg). The DMA state machine is implemented using a case statement (not shown in the code snippet).

  5. 5

    However, the above code [REF-1394] allows the values of pmpaddr_i and pmpcfg_i to be changed through DMA's input ports. This causes a race condition and will enable attackers to access sensitive addresses that the configuration is not associated with. Attackers can initialize the DMA access process (CTRL_IDLE) using pmpcfg_i for a non-privileged PMP address (pmpaddr_i). Then during the loading state (CTRL_LOAD), attackers can replace the non-privileged address in pmpaddr_i with a privileged address without the requisite authorized access configuration. To fix this issue (see [REF-1395]), the value of the pmpaddr_i and pmpcfg_i signals should be stored in local registers (pmpaddr_reg and pmpcfg_reg at the start of the DMA access process and the pmp module should reference those registers instead of the signals directly. The values of the registers can only be updated at the start (CTRL_IDLE) or the end (CTRL_DONE) of the DMA access process, which prevents attackers from changing the PMP address in the middle of the DMA access process.

Verwundbares Codebeispiel

Vulnerable Verilog

The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.

Verwundbar Verilog 
// 2x1 Multiplexor using logic-gates

 module glitchEx(

```
   input wire in0, in1, sel,
   output wire z
 );
 wire not_sel;
 wire and_out1, and_out2;
 assign not_sel = ~sel;
 assign and_out1 = not_sel & in0;
 assign and_out2 = sel & in1;
 // Buggy line of code:
 assign z = and_out1 | and_out2; // glitch in signal z
 endmodule
Sicheres Codebeispiel

Secure Verilog

The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.

Sicher Verilog 
assign z <= and_out1 or and_out2 or (in0 and in1);
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Präventions-Checkliste

How to prevent CWE-1298

  • Architecture and Design Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.
  • Implementation Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.
Erkennungssignale

How to detect CWE-1298

SAST High

Führe statische Analyse (SAST) auf der Codebasis aus und suche im Datenfluss nach dem unsicheren Muster.

DAST Moderate

Führe dynamische Application-Security-Tests gegen den Live-Endpoint aus.

Runtime Moderate

Beobachte Runtime-Logs auf ungewöhnliche Exception-Traces, fehlerhafte Eingaben oder Versuche, Autorisierung zu umgehen.

Code review Moderate

Code Review: Markiere jeden neuen Code, der Eingaben von dieser Oberfläche ohne validierte Framework-Helper verarbeitet.

Plexicus Auto-Fix

Plexicus erkennt CWE-1298 automatisch und öffnet in unter 60 Sekunden einen Fix-PR.

Codex Remedium scannt jeden Commit, identifiziert genau diese Schwachstelle und liefert einen reviewer-ready Pull Request mit dem Patch. Keine Tickets. Keine Hand-offs.

Demo anfordern Plexicus kostenlos testen
Häufig gestellte Fragen

Frequently asked questions

Was ist CWE-1298?

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.

Wie gravierend ist CWE-1298?

MITRE hat für diese Schwachstelle keine Exploit-Wahrscheinlichkeit veröffentlicht. Behandle sie als mittlere Auswirkung, bis dein Threat Model anderes belegt.

Welche Sprachen oder Plattformen sind von CWE-1298 betroffen?

MITRE lists the following affected platforms: Verilog, VHDL, System on Chip.

Wie kann ich CWE-1298 verhindern?

Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions. Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

Wie erkennt und behebt Plexicus CWE-1298?

Die SAST-Engine von Plexicus erkennt die Datenfluss-Signatur von CWE-1298 bei jedem Commit. Bei einem Treffer öffnet unser Codex-Remedium-Agent einen Fix-PR mit korrigiertem Code, Tests und einer einzeiligen Zusammenfassung für den Reviewer.

Wo erfahre ich mehr über CWE-1298?

MITRE veröffentlicht die kanonische Definition unter https://cwe.mitre.org/data/definitions/1298.html. Für ergänzende Hinweise kannst du auch die OWASP- und NIST-Dokumentation heranziehen.

Verwandte Schwachstellen

Weaknesses related to CWE-1298

CWE-362 Parent

Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')

A race condition occurs when multiple processes or threads access a shared resource simultaneously without proper coordination, creating a…

CWE-1223 Sibling

Race Condition for Write-Once Attributes

This vulnerability occurs when an untrusted software component wins a race condition and writes to a hardware register before the trusted…

CWE-364 Sibling

Signal Handler Race Condition

A signal handler race condition occurs when a program's signal handling routine is vulnerable to timing issues, allowing its state to be…

CWE-366 Sibling

Race Condition within a Thread

This vulnerability occurs when two or more threads within the same application access and manipulate a shared resource (like a variable,…

CWE-367 Sibling

Time-of-check Time-of-use (TOCTOU) Race Condition

This vulnerability occurs when a program verifies a resource's state (like a file's permissions or existence) but then uses it after that…

CWE-368 Sibling

Context Switching Race Condition

This vulnerability occurs when an application switches between different security contexts (like privilege levels or domains) using a…

CWE-421 Sibling

Race Condition During Access to Alternate Channel

A race condition occurs when an application opens a secondary communication channel intended for an authorized user, but fails to secure…

CWE-689 Sibling

Permission Race Condition During Resource Copy

This vulnerability occurs when a system copies a file or resource but delays setting its final permissions until the entire copy operation…

Ressourcen

Further reading

Bereit, wenn du es bist

Schluss mit dem Bezahlen pro Entwickler.
Schließ den Kreislauf.

Plexicus ist die KI-native ASPM, die scannt, filtert, fixt, pentestet und erklärt — autonom. Unbegrenzte Entwickler, unbegrenzte Repos, Fair-Use-KI-Aktionen. Echter kostenloser Tarif, €269/mo jährlich, wenn du bereit bist.

Kostenlos starten Demo buchen