CWE-1224 Base Incomplete

Improper Restriction of Write-Once Bit Fields

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Definition

What is CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.
Hardware designs use special write-once or 'sticky' bit fields in control registers to lock critical settings. These are intended to be configured only once—typically during initial boot by trusted firmware—and then become permanently read-only. This mechanism is a fundamental security feature that prevents runtime software or malware from altering secure hardware configurations, such as memory protection or debug access controls. When this restriction fails, software can repeatedly overwrite these bits. A common implementation flaw is creating 'write-1-once' logic instead of true 'write-once' protection. In this flawed scenario, a bit might only become locked after being set to '1,' leaving it vulnerable if set to '0' first or allowing toggling between values. This exposes the hardware to privilege escalation, system compromise, or bypass of critical security boundaries.
Auswirkungen in der Praxis

Real-world CVEs caused by CWE-1224

Bisher sind in MITREs Katalog keine öffentlichen CVE-Referenzen mit dieser CWE verknüpft.

Wie Angreifer es ausnutzen

Angreiferpfad Schritt für Schritt

  1. 1

    Identifiziere einen Codepfad, der nicht vertrauenswürdige Eingaben ohne Validierung verarbeitet.

  2. 2

    Erzeuge eine Payload, die das unsichere Verhalten auslöst — Injection, Traversal, Overflow oder Logik-Missbrauch.

  3. 3

    Liefere die Payload über einen normalen Request aus und beobachte die Reaktion der Anwendung.

  4. 4

    Iteriere, bis die Antwort Daten preisgibt, Angreifer-Code ausführt oder Berechtigungen eskaliert.

Verwundbares Codebeispiel

Vulnerable Verilog

Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value. This implementation can be for a register that is defined by specification to be a write-once register, since the write_once_status field gets written by input data bit 0 on first write.

Verwundbar Verilog 
module register_write_once_example
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn,
 input write,
 output reg [15:0] Data_out 
 );

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn)

```
   if (~ip_resetn)
   begin
  	 Data_out <= 16'h0000;
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status)
   begin
  	 Data_out <= Data_in & 16'hFFFE;
  	 Write_once_status <= Data_in[0]; // Input bit 0 sets Write_once_status
   end
   else if (~write)
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule
Sicheres Codebeispiel

Secure Verilog

The above example only locks further writes if write_once_status bit is written to one. So it acts as write_1-Once instead of the write-once attribute.

Sicher Verilog 
module register_write_once_example 
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn, 
 input write, 
 output reg [15:0] Data_out 
 ); 

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn) 

```
   if (~ip_resetn) 
   begin 
  	 Data_out <= 16'h0000; 
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status) 
   begin 
  	 Data_out <= Data_in & 16'hFFFE; 
  	 Write_once_status <= 1'b1; // Write once status set on first write, independent of input 
   end 
   else if (~write) 
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Präventions-Checkliste

How to prevent CWE-1224

  • Architecture and Design During hardware design all register write-once or sticky fields must be evaluated for proper configuration.
  • Testing The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.
Erkennungssignale

How to detect CWE-1224

SAST High

Führe statische Analyse (SAST) auf der Codebasis aus und suche im Datenfluss nach dem unsicheren Muster.

DAST Moderate

Führe dynamische Application-Security-Tests gegen den Live-Endpoint aus.

Runtime Moderate

Beobachte Runtime-Logs auf ungewöhnliche Exception-Traces, fehlerhafte Eingaben oder Versuche, Autorisierung zu umgehen.

Code review Moderate

Code Review: Markiere jeden neuen Code, der Eingaben von dieser Oberfläche ohne validierte Framework-Helper verarbeitet.

Plexicus Auto-Fix

Plexicus erkennt CWE-1224 automatisch und öffnet in unter 60 Sekunden einen Fix-PR.

Codex Remedium scannt jeden Commit, identifiziert genau diese Schwachstelle und liefert einen reviewer-ready Pull Request mit dem Patch. Keine Tickets. Keine Hand-offs.

Demo anfordern Plexicus kostenlos testen
Häufig gestellte Fragen

Frequently asked questions

Was ist CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Wie gravierend ist CWE-1224?

MITRE hat für diese Schwachstelle keine Exploit-Wahrscheinlichkeit veröffentlicht. Behandle sie als mittlere Auswirkung, bis dein Threat Model anderes belegt.

Welche Sprachen oder Plattformen sind von CWE-1224 betroffen?

MITRE lists the following affected platforms: Verilog, VHDL, System on Chip.

Wie kann ich CWE-1224 verhindern?

During hardware design all register write-once or sticky fields must be evaluated for proper configuration. The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

Wie erkennt und behebt Plexicus CWE-1224?

Die SAST-Engine von Plexicus erkennt die Datenfluss-Signatur von CWE-1224 bei jedem Commit. Bei einem Treffer öffnet unser Codex-Remedium-Agent einen Fix-PR mit korrigiertem Code, Tests und einer einzeiligen Zusammenfassung für den Reviewer.

Wo erfahre ich mehr über CWE-1224?

MITRE veröffentlicht die kanonische Definition unter https://cwe.mitre.org/data/definitions/1224.html. Für ergänzende Hinweise kannst du auch die OWASP- und NIST-Dokumentation heranziehen.

Verwandte Schwachstellen

Weaknesses related to CWE-1224

CWE-284 Parent

Improper Access Control

The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.

CWE-1191 Sibling

On-Chip Debug and Test Interface With Improper Access Control

This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…

CWE-1220 Sibling

Insufficient Granularity of Access Control

This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…

CWE-1231 Sibling

Improper Prevention of Lock Bit Modification

This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to…

CWE-1233 Sibling

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to…

CWE-1252 Sibling

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…

CWE-1257 Sibling

Improper Access Control Applied to Mirrored or Aliased Memory Regions

This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to…

CWE-1259 Sibling

Improper Restriction of Security Token Assignment

This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…

CWE-1260 Sibling

Improper Handling of Overlap Between Protected Memory Ranges

This vulnerability occurs when a system incorrectly allows different memory protection ranges to overlap. This flaw can let attackers…

Ressourcen

Further reading

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