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Security-Sensitive Hardware Controls with Missing Lock Bit Protection

Stable Base
Structure: Simple
Description

This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to prevent writes to all registers that can alter the protected system settings. Essentially, the security mechanism is incomplete, allowing software to bypass it and modify sensitive hardware configurations.

Extended Description

Many integrated circuits and hardware IPs contain configuration controls that are set by trusted firmware, like a BIOS or bootloader, immediately after a device powers on. To prevent later tampering, a trusted lock bit is often used to permanently disable writes to a specific set of protected registers. The expectation is that once this lock is engaged, the critical hardware configuration—such as memory or security unit settings—is frozen and cannot be changed. However, if this lock bit does not effectively write-protect every single register or control that can influence the protected configuration, the security model breaks. An attacker with software access can then locate and manipulate these unprotected controls to alter the hardware's secure state, potentially undermining system integrity and bypassing intended security boundaries.
Common Consequences 1
Scope: Access Control

Impact: Modify Memory

System Configuration protected by the lock bit can be modified even when the lock is set.
Detection Methods 1
Manual AnalysisHigh
Set the lock bit. Attempt to modify the information protected by the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.
Potential Mitigations 1
Phase: Architecture and DesignImplementationTesting
- Security lock bit protections must be reviewed for design inconsistency and common weaknesses. - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.
Demonstrative Examples 1
Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by the firmware.

Code Example:

Bad
Other
RegisterField description
CRITICAL_TEMP_LIMIT[31:8] Reserved field; Read only; Default 0 [7:0] Critical temp 0-255 Centigrade; Read-write-lock; Default 125
TEMP_SENSOR_CALIB[31:0] Thermal sensor calibration data. A slope value used to map sensor reading to a degree Centigrade. Read-write; Default 25
TEMP_SENSOR_LOCK[31:1] Reserved field; Read only; Default 0 [0] Lock bit, locks CRITICAL_TEMP_LIMIT register; Write-1-once; Default 0
TEMP_HW_SHUTDOWN[31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on a critical temperature detection; Read-write; Default 0
CURRENT_TEMP[31:8] Reserved field; Read only; Default 0 [7:0] Current Temp 0-255 Centigrade; Read-only; Default 0
In this example note that only the CRITICAL_TEMP_LIMIT register is protected by the TEMP_SENSOR_LOCK bit, while the security design intent is to protect any modification of the critical temperature detection and response. The response of the system, if the system heats to a critical temperature, is controlled by TEMP_HW_SHUTDOWN bit [1], which is not lockable. Also, the TEMP_SENSOR_CALIB register is not protected by the lock bit. By modifying the temperature sensor calibration, the conversion of the sensor data to a degree centigrade can be changed, such that the current temperature will never be detected to exceed critical temperature value programmed by the protected lock. Similarly, by modifying the TEMP_HW_SHUTDOWN.Enable bit, the system response detection of the current temperature exceeding critical temperature can be disabled.

Code Example:

Good
Other

Change TEMP_HW_SHUTDOWN and TEMP_SENSOR_CALIB controls to be locked by TEMP_SENSOR_LOCK.

| | | | TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. A slope value used to map sensor reading to a degree Centigrade. Read-write-Lock; Default 25; Locked by TEMP_SENSOR_LOCK bit[0] | | TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on critical temperature detection; Read-write-Lock; Default 0; Locked by TEMP_SENSOR_LOCK bit[0] |
Observed Examples 2
CVE-2018-9085Certain servers leave a write protection lock bit unset after boot, potentially allowing modification of parts of flash memory.
CVE-2014-8273Chain: chipset has a race condition (Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')) between when an interrupt handler detects an attempt to write-enable the BIOS (in violation of the lock bit), and when the handler resets the write-enable bit back to 0, allowing attackers to issue BIOS writes during the timing window [REF-1237].
References 1
Intel BIOS locking mechanism contains race condition that enables write protection bypass
CERT Coordination Center
05-01-2015
https://www.kb.cert.org/vuls/id/766164/
ID: REF-1237
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Architecture and Design
Implementation
Related Attack Patterns
Related Weaknesses
ChildOf: Improper Access Control (CWE-284)
ChildOf: Improper Locking (CWE-667)