CWE-1231 Base Stable

Improper Prevention of Lock Bit Modification

This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to properly prevent that lock bit from being changed after it…

Definition

What is CWE-1231?

This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to properly prevent that lock bit from being changed after it has been enabled. This design flaw allows attackers to bypass hardware-enforced security restrictions.

In hardware design and system-on-chip (SoC) architectures, a lock bit acts as a hardware-enforced security switch. Trusted firmware like a BIOS or bootloader typically sets this bit during initialization to permanently disable writes to protected configuration registers—such as those controlling debug modes, memory protection, or secure boot settings. Once locked, these settings should become immutable to prevent runtime tampering. If the implementation contains flaws—like allowing the lock bit itself to be written, clearing it via a side channel, or failing to verify its state—attackers can reverse the lock. This effectively unlocks the protected resources, enabling unauthorized reconfiguration, privilege escalation, or extraction of sensitive data that the hardware was designed to guard.

Auswirkungen in der Praxis

Real-world CVEs caused by CWE-1231

CVE-2017-6283

chip reset clears critical read/write lock permissions for RSA function

Wie Angreifer es ausnutzen

Angreiferpfad Schritt für Schritt

1
Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by firmware, and then the register needs to be locked (TEMP_SENSOR_LOCK).
2
In this example, note that if the system heats to critical temperature, the response of the system is controlled by the TEMP_HW_SHUTDOWN bit [1], which is not lockable. Thus, the intended security property of the critical temperature sensor cannot be fully protected, since software can misconfigure the TEMP_HW_SHUTDOWN register even after the lock bit is set to disable the shutdown response.
3
The following example code is a snippet from the register locks inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1350]. Register locks help prevent SoC peripherals' registers from malicious use of resources. The registers that can potentially leak secret data are locked by register locks.
4
In the vulnerable code, the reglk_mem is used for locking information. If one of its bits toggle to 1, the corresponding peripheral's registers will be locked. In the context of the HACK@DAC System-on-Chip (SoC), it is pertinent to note the existence of two distinct categories of reset signals.
5
First, there is a global reset signal denoted as "rst_ni," which possesses the capability to simultaneously reset all peripherals to their respective initial states.

Verwundbares Codebeispiel

Vulnerable Other

Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by firmware, and then the register needs to be locked (TEMP_SENSOR_LOCK).

Verwundbar Other

| Register | Field description | 
| --- | --- |
| CRITICAL_TEMP_LIMIT | [31:8] Reserved field; Read only; Default 0  [7:0] Critical temp 0-255 Centigrade; Read-write-lock; Default 125 |
| TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. Slope value used to map sensor reading to degrees Centigrade.  |
| TEMP_SENSOR_LOCK | [31:1] Reserved field; Read only; Default 0  [0] Lock bit, locks CRITICAL_TEMP_LIMIT and TEMP_SENSOR_CALIB registers; Write-1-once; Default 0 |
| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0  [1] Enable hardware shutdown on critical temperature detection; Read-write; Default 0 |
| CURRENT_TEMP | [31:8] Reserved field; Read only; Default 0  [7:0] Current Temp 0-255 Centigrade; Read-only; Default 0 |

Sicheres Codebeispiel

Secure Other

In this example, note that if the system heats to critical temperature, the response of the system is controlled by the TEMP_HW_SHUTDOWN bit [1], which is not lockable. Thus, the intended security property of the critical temperature sensor cannot be fully protected, since software can misconfigure the TEMP_HW_SHUTDOWN register even after the lock bit is set to disable the shutdown response.

Sicher Other

To fix this weakness, one could change the TEMP_HW_SHUTDOWN field to be locked by TEMP_SENSOR_LOCK.

|  | 
|
| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0   [1] Enable hardware shutdown on critical temperature detection; Read-write-Lock; Default 0 [0] Locked by TEMP_SENSOR_LOCK |

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Präventions-Checkliste

How to prevent CWE-1231

Architecture and Design / Implementation / Testing - Security lock bit protections must be reviewed for design inconsistency and common weaknesses. - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.

Erkennungssignale

How to detect CWE-1231

Manual Analysis High

Set the lock bit. Power cycle the device. Attempt to clear the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.

Plexicus Auto-Fix

Plexicus erkennt CWE-1231 automatisch und öffnet in unter 60 Sekunden einen Fix-PR.

Codex Remedium scannt jeden Commit, identifiziert genau diese Schwachstelle und liefert einen reviewer-ready Pull Request mit dem Patch. Keine Tickets. Keine Hand-offs.

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Häufig gestellte Fragen

Frequently asked questions

Was ist CWE-1231?

Wie gravierend ist CWE-1231?

MITRE hat für diese Schwachstelle keine Exploit-Wahrscheinlichkeit veröffentlicht. Behandle sie als mittlere Auswirkung, bis dein Threat Model anderes belegt.

Welche Sprachen oder Plattformen sind von CWE-1231 betroffen?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Not Technology-Specific.

Wie kann ich CWE-1231 verhindern?

- Security lock bit protections must be reviewed for design inconsistency and common weaknesses. - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.

Wie erkennt und behebt Plexicus CWE-1231?

Die SAST-Engine von Plexicus erkennt die Datenfluss-Signatur von CWE-1231 bei jedem Commit. Bei einem Treffer öffnet unser Codex-Remedium-Agent einen Fix-PR mit korrigiertem Code, Tests und einer einzeiligen Zusammenfassung für den Reviewer.

Wo erfahre ich mehr über CWE-1231?

MITRE veröffentlicht die kanonische Definition unter https://cwe.mitre.org/data/definitions/1231.html. Für ergänzende Hinweise kannst du auch die OWASP- und NIST-Dokumentation heranziehen.

Verwandte Schwachstellen

Weaknesses related to CWE-1231

CWE-284 Parent

Improper Access Control

The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.

CWE-1191 Sibling

On-Chip Debug and Test Interface With Improper Access Control

This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…

CWE-1220 Sibling

Insufficient Granularity of Access Control

This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…

CWE-1224 Sibling

Improper Restriction of Write-Once Bit Fields

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented,…

CWE-1233 Sibling

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to…

CWE-1252 Sibling

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…

CWE-1257 Sibling

Improper Access Control Applied to Mirrored or Aliased Memory Regions

This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to…

CWE-1259 Sibling

Improper Restriction of Security Token Assignment

This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…

CWE-1260 Sibling

Improper Handling of Overlap Between Protected Memory Ranges

This vulnerability occurs when a system incorrectly allows different memory protection ranges to overlap. This flaw can let attackers…

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