Improper Handling of Overlap Between Protected Memory Ranges

What is CWE-1260?

Angreiferpfad Schritt für Schritt

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   For example, consider a design with a 16-bit address that has two software privilege levels: Privileged_SW and Non_privileged_SW. To isolate the system memory regions accessible by these two privilege levels, the design supports three memory regions: Region_0, Region_1, and Region_2. Each region is defined by two 32 bit registers: its range and its access policy. - Address_range[15:0]: specifies the Base address of the region - Address_range[31:16]: specifies the size of the region - Access_policy[31:0]: specifies what types of software can access a region and which actions are allowed Certain bits of the access policy are defined symbolically as follows: - Access_policy.read_np: if set to one, allows reads from Non_privileged_SW - Access_policy.write_np: if set to one, allows writes from Non_privileged_SW - Access_policy.execute_np: if set to one, allows code execution by Non_privileged_SW - Access_policy.read_p: if set to one, allows reads from Privileged_SW - Access_policy.write_p: if set to one, allows writes from Privileged_SW - Access_policy.execute_p: if set to one, allows code execution by Privileged_SW For any requests from software, an address-protection filter checks the address range and access policies for each of the three regions, and only allows software access if all three filters allow access. Consider the following goals for access control as intended by the designer: - Region_0 & Region_1: registers are programmable by Privileged_SW - Region_2: registers are programmable by Non_privileged_SW The intention is that Non_privileged_SW cannot modify memory region and policies defined by Privileged_SW in Region_0 and Region_1. Thus, it cannot read or write the memory regions that Privileged_SW is using.

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   This design could be improved in several ways.

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   The example code below is taken from the IOMMU controller module of the HACK@DAC'19 buggy CVA6 SoC [REF-1338]. The static memory map is composed of a set of Memory-Mapped Input/Output (MMIO) regions covering different IP agents within the SoC. Each region is defined by two 64-bit variables representing the base address and size of the memory region (XXXBase and XXXLength).

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   In this example, we have 12 IP agents, and only 4 of them are called out for illustration purposes in the code snippets. Access to the AES IP MMIO region is considered privileged as it provides access to AES secret key, internal states, or decrypted data.

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   The vulnerable code allows the overlap between the protected MMIO region of the AES peripheral and the unprotected UART MMIO region. As a result, unprivileged users can access the protected region of the AES IP. In the given vulnerable example UART MMIO region starts at address 64'h1000_0000 and ends at address 64'h1011_1000 (UARTBase is 64'h1000_0000, and the size of the region is provided by the UARTLength of 64'h0011_1000).

How to prevent CWE-1260

• Architecture and Design Ensure that memory regions are isolated as intended and that access control (read/write) policies are used by hardware to protect privileged software.
• Implementation For all of the programmable memory protection regions, the memory protection unit (MPU) design can define a priority scheme. For example: if three memory regions can be programmed (Region_0, Region_1, and Region_2), the design can enforce a priority scheme, such that, if a system address is within multiple regions, then the region with the lowest ID takes priority and the access-control policy of that region will be applied. In some MPU designs, the priority scheme can also be programmed by trusted software. Hardware logic or trusted firmware can also check for region definitions and block programming of memory regions with overlapping addresses. The memory-access-control-check filter can also be designed to apply a policy filter to all of the overlapping ranges, i.e., if an address is within Region_0 and Region_1, then access to this address is only granted if both Region_0 and Region_1 policies allow the access.

Frequently asked questions

Further reading

• MITRE — offizielle CWE-1260 https://cwe.mitre.org/data/definitions/1260.html
• The Memory Sinkhole https://github.com/xoreaxeaxeax/sinkhole/blob/master/us-15-Domas-TheMemorySinkhole-wp.pdf
• Hackatdac19 ariane_soc_pkg.sv https://github.com/HACK-EVENT/hackatdac19/blob/619e9fb0ef32ee1e01ad76b8732a156572c65700/tb/ariane_soc_pkg.sv#L44:L62
• csr_regfile.sv https://github.com/openhwgroup/cva6/blob/7951802a0147aedb21e8f2f6dc1e1e9c4ee857a2/src/csr_regfile.sv#L45