Using an external debugger, send write transactions to mirrored regions to test if original, write-protected regions are modified. Similarly, send read transactions to mirrored regions to test if the original, read-protected signals can be read.
CWE-1312 Base Draft
Missing Protection for Mirrored Regions in On-Chip Fabric Firewall
An on-chip fabric firewall fails to apply its security rules to mirrored memory or MMIO regions, only protecting the primary address range. This allows attackers to bypass read/write restrictions by…
Definition
What is CWE-1312?
An on-chip fabric firewall fails to apply its security rules to mirrored memory or MMIO regions, only protecting the primary address range. This allows attackers to bypass read/write restrictions by targeting the unprotected mirrored copies.
Many on-chip fabrics use mirrored memory regions—duplicate copies of original data—to provide redundancy and fault tolerance. However, a critical oversight occurs when the fabric's firewall enforces access controls only on the primary region and neglects to extend those same protections to the mirrored copies. This creates a security gap where the mirrored regions become unprotected backdoors to the same sensitive data.
Attackers can exploit this gap to completely bypass the intended security policy. By simply reading from or writing to the mirrored address, they can leak confidential information from the original region or corrupt its data, undermining the firewall's entire purpose. To prevent this, any firewall rule for a primary memory region must be automatically and consistently applied to all of its mirrored counterparts.
Auswirkungen in der Praxis
Real-world CVEs caused by CWE-1312
Bisher sind in MITREs Katalog keine öffentlichen CVE-Referenzen mit dieser CWE verknüpft.
Wie Angreifer es ausnutzen
Angreiferpfad Schritt für Schritt
- 1
A memory-controller IP block is connected to the on-chip fabric in a System on Chip (SoC). The memory controller is configured to divide the memory into four parts: one original and three mirrored regions inside the memory. The upper two bits of the address indicate which region is being addressed. 00 indicates the original region and 01, 10, and 11 are used to address the mirrored regions. All four regions operate in a lock-step manner and are always synchronized. The firewall in the on-chip fabric is programmed to protect the assets in the memory.
- 2
The firewall only protects the original range but not the mirrored regions.
- 3
The attacker (as an unprivileged user) sends a write transaction to the mirrored region. The mirrored region has an address with the upper two bits set to "10" and the remaining bits of the address pointing to an asset. The firewall does not block this write transaction. Once the write is successful, contents in the protected-memory region are also updated. Thus, the attacker can bypass existing, memory protections.
- 4
Firewall should protect mirrored regions.
Verwundbares Codebeispiel
Vulnerable pseudo
MITRE hat kein Codebeispiel für diese CWE veröffentlicht. Das untenstehende Muster ist illustrativ — kanonische Referenzen findest du unter Ressourcen.
// Example pattern — see MITRE for the canonical references.
function handleRequest(input) {
// Untrusted input flows directly into the sensitive sink.
return executeUnsafe(input);
} Sicheres Codebeispiel
Secure pseudo
// Validate, sanitize, or use a safe API before reaching the sink.
function handleRequest(input) {
const safe = validateAndEscape(input);
return executeWithGuards(safe);
} What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Präventions-Checkliste
How to prevent CWE-1312
- Architecture and Design The fabric firewall should apply the same protections as the original region to the mirrored regions.
- Implementation The fabric firewall should apply the same protections as the original region to the mirrored regions.
Erkennungssignale
How to detect CWE-1312
Plexicus erkennt CWE-1312 automatisch und öffnet in unter 60 Sekunden einen Fix-PR.
Codex Remedium scannt jeden Commit, identifiziert genau diese Schwachstelle und liefert einen reviewer-ready Pull Request mit dem Patch. Keine Tickets. Keine Hand-offs.
Häufig gestellte Fragen Was ist CWE-1312?
Wie gravierend ist CWE-1312?
Welche Sprachen oder Plattformen sind von CWE-1312 betroffen?
Wie kann ich CWE-1312 verhindern?
Wie erkennt und behebt Plexicus CWE-1312?
Wo erfahre ich mehr über CWE-1312?
Frequently asked questions
Was ist CWE-1312?
An on-chip fabric firewall fails to apply its security rules to mirrored memory or MMIO regions, only protecting the primary address range. This allows attackers to bypass read/write restrictions by targeting the unprotected mirrored copies.
Wie gravierend ist CWE-1312?
MITRE hat für diese Schwachstelle keine Exploit-Wahrscheinlichkeit veröffentlicht. Behandle sie als mittlere Auswirkung, bis dein Threat Model anderes belegt.
Welche Sprachen oder Plattformen sind von CWE-1312 betroffen?
MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Not Technology-Specific.
Wie kann ich CWE-1312 verhindern?
The fabric firewall should apply the same protections as the original region to the mirrored regions. The fabric firewall should apply the same protections as the original region to the mirrored regions.
Wie erkennt und behebt Plexicus CWE-1312?
Die SAST-Engine von Plexicus erkennt die Datenfluss-Signatur von CWE-1312 bei jedem Commit. Bei einem Treffer öffnet unser Codex-Remedium-Agent einen Fix-PR mit korrigiertem Code, Tests und einer einzeiligen Zusammenfassung für den Reviewer.
Wo erfahre ich mehr über CWE-1312?
MITRE veröffentlicht die kanonische Definition unter https://cwe.mitre.org/data/definitions/1312.html. Für ergänzende Hinweise kannst du auch die OWASP- und NIST-Dokumentation heranziehen.
Verwandte Schwachstellen
Weaknesses related to CWE-1312
CWE-284 Parent
Improper Access Control
The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.
CWE-1191 Sibling
On-Chip Debug and Test Interface With Improper Access Control
This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…
CWE-1220 Sibling
Insufficient Granularity of Access Control
This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…
CWE-1224 Sibling
Improper Restriction of Write-Once Bit Fields
This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented,…
CWE-1231 Sibling
Improper Prevention of Lock Bit Modification
This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to…
CWE-1233 Sibling
Security-Sensitive Hardware Controls with Missing Lock Bit Protection
This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to…
CWE-1252 Sibling
CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…
CWE-1257 Sibling
Improper Access Control Applied to Mirrored or Aliased Memory Regions
This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to…
CWE-1259 Sibling
Improper Restriction of Security Token Assignment
This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…
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