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Failure to Disable Reserved Bits

Incomplete Base
Structure: Simple
Description

This vulnerability occurs when reserved bits in a hardware design are left active in production. Designers sometimes use these bits for debugging or future features, but if not disabled, attackers can manipulate them to compromise the hardware's state.

Extended Description

Reserved bits are placeholders in a hardware design intended for future use and should have no functional purpose in the current version. However, to accelerate development or testing, designers might secretly enable logic connected to these bits for debugging or to prototype new features. Leaving this logic active creates a hidden backdoor that attackers can discover and exploit. When these bits remain enabled in production hardware, an adversary with access can write to them to trigger this hidden logic. This allows them to bypass security controls, alter configurations, or force the hardware into unsupported and potentially harmful states that were never intended for the released product.
Common Consequences 1
Scope: ConfidentialityIntegrityAvailabilityAccess ControlAccountabilityAuthenticationAuthorizationNon-Repudiation

Impact: Varies by Context

This type of weakness all depends on the capabilities of the logic being controlled or configured by the reserved bits.
Potential Mitigations 2
Phase: Architecture and DesignImplementation
Include a feature to disable reserved bits.
Phase: Integration
Any writes to these reserve bits are blocked (e.g., ignored, access-protected, etc.), or an exception can be asserted.
Demonstrative Examples 1
Assume a hardware Intellectual Property (IP) has address space 0x0-0x0F for its configuration registers, with the last one labeled reserved (i.e. 0x0F). Therefore inside the Finite State Machine (FSM), the code is as follows:

Code Example:

Bad
Verilog

reg gpio_out = 0; //gpio should remain low for normal operation

case (register_address)

verilog
An adversary may perform writes to reserved address space in hopes of changing the behavior of the hardware. In the code above, the GPIO pin should remain low for normal operation. However, it can be asserted by accessing the reserved address space (0x0F). This may be a concern if the GPIO state is being used as an indicator of health (e.g. if asserted the hardware may respond by shutting down or resetting the system, which may not be the correct action the system should perform). In the code below, the condition "register_address = 0X0F" is commented out, and a default is provided that will catch any values of register_address not explicitly accounted for and take no action with regards to gpio_out. This means that an attacker who is able to write 0X0F to register_address will not enable any undocumented "features" in the process.

Code Example:

Good
Verilog

reg gpio_out = 0; //gpio should remain low for normal operation

case (register_address)

verilog
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
System on Chip : Undetermined
Modes of Introduction
Architecture and Design
Implementation
Documentation
Related Attack Patterns
Related Weaknesses
ChildOf: Improper Adherence to Coding Standards (CWE-710)