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Sensitive Non-Volatile Information Not Protected During Debug

Incomplete Base
Structure: Simple
Description

This vulnerability occurs when security-critical data stored in hardware fuses is left unprotected and accessible during debug modes.

Extended Description

Modern chips store highly sensitive data—like encryption keys, root secrets, and unique manufacturer codes—in permanent hardware fuses. When the device powers on, this information is loaded into temporary registers or on-chip memory for runtime use. While normal software access to these locations is usually restricted, debug interfaces often bypass these protections entirely. During debug or testing operations, these temporary storage locations remain exposed, allowing anyone with debug access to read the sensitive fuse data. This creates a significant hardware-level security gap, as an attacker can extract foundational secrets that underpin the device's entire security model, potentially compromising encryption, authentication, and secure boot processes.
Common Consequences 1
Scope: ConfidentialityAccess Control

Impact: Modify MemoryBypass Protection Mechanism
Potential Mitigations 1
Phase: Architecture and DesignImplementation
Disable access to security-sensitive information stored in fuses directly and also reflected from temporary storage locations when in debug mode.
Demonstrative Examples 2
Sensitive manufacturing data (such as die information) are stored in fuses. When the chip powers on, these values are read from the fuses and stored in microarchitectural registers. These registers are only given read access to trusted software running on the core. Untrusted software running on the core is not allowed to access these registers.

Code Example:

Bad
Other
other

Code Example:

Good
Other
other
The example code below is taken from one of the AES cryptographic accelerators of the HACK@DAC'21 buggy OpenPiton SoC [REF-1366]. The operating system (OS) uses three AES keys to encrypt and decrypt sensitive data using this accelerator. These keys are sensitive data stored in fuses. The security of the OS will be compromised if any of these AES keys are leaked. During system bootup, these AES keys are sensed from fuses and stored in temporary hardware registers of the AES peripheral. Access to these temporary registers is disconnected during the debug state to prevent them from leaking through debug access. In this example (see the vulnerable code source), the registers key0, key1, and key2 are used to store the three AES keys (which are accessed through key_big0, key_big1, and key_big2 signals). The OS selects one of these three keys through the key_big signal, which is used by the AES engine.

Code Example:

Bad
Verilog

... assign key_big0 = debug_mode_i ? 192'b0 : {key0[0], key0[1], key0[2], key0[3], key0[4], key0[5]};

assign key_big1 = debug_mode_i ? 192'b0 : {key1[0], key1[1], key1[2], key1[3], key1[4], key1[5]};

assign key_big2 = {key2[0], key2[1], key2[2],

key2[3], key2[4], key2[5]}; ...

assign key_big = key_sel[1] ? key_big2 : ( key_sel[0] ?

key_big1 : key_big0 ); ...

The above code illustrates an instance of a vulnerable implementation for blocking AES key mechanism when the system is in debug mode (i.e., when debug_mode_i is asserted). During debug mode, key accesses through key_big0 and key_big1 are effectively disconnected, as their values are set to zero. However, the key accessed via the key_big2 signal remains accessible, creating a potential pathway for sensitive fuse data leakage, specifically AES key2, during debug mode. Furthermore, even though it is not strictly necessary to disconnect the key_big signal when entering debug mode (since disconnecting key_big0, key_big1, and key_big2 will inherently disconnect key_big), it is advisable, in line with the defense-in-depth strategy, to also sever the connection to key_big. This additional security measure adds an extra layer of protection and safeguards the AES keys against potential future modifications to the key_big logic.
To mitigate this, disconnect access through key_big2 and key_big during debug mode [REF-1367].

Code Example:

Good
Verilog

... assign key_big0 = debug_mode_i ? 192'b0 : {key0[0], key0[1], key0[2], key0[3], key0[4], key0[5]};

assign key_big1 = debug_mode_i ? 192'b0 : {key1[0], key1[1], key1[2], key1[3], key1[4], key1[5]};

assign key_big2 = debug_mode_i ? 192'b0 : {key2[0], key2[1], key2[2], key2[3], key2[4], key2[5]}; ... assign key_big = debug_mode_i ? 192'b0 : ( key_sel[1] ? key_big2 : ( key_sel[0] ? key_big1 : key_big0 ) ); ...
References 2
aes0_wrapper.sv
2021
https://github.com/HACK-EVENT/hackatdac21/blob/71103971e8204de6a61afc17d3653292517d32bf/piton/design/chip/tile/ariane/src/aes0/aes0_wrapper.sv#L56C1-L57C1(2023-07-15)
ID: REF-1366
fix cwe_1243 in aes0_wrapper.sv
2021
https://github.com/HACK-EVENT/hackatdac21/blob/cde1d9d6888bffab21d4b405ccef61b19c58dd3c/piton/design/chip/tile/ariane/src/aes0/aes0_wrapper.sv#L56(2023-09-28)
ID: REF-1367
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Architecture and Design
Implementation
Related Attack Patterns
Related Weaknesses
ChildOf: Improper Physical Access Control (CWE-1263)