This vulnerability occurs when hardware logic contains flawed Finite State Machines (FSMs). Attackers can exploit these design errors to force the system into an undefined or unstable condition, potentially leading to a denial of service (DoS) or allowing privilege escalation.
Finite State Machines are critical for managing a system's security posture and operational flow. They often control access to sensitive data and govern secure operations. If an FSM is poorly designed—for example, by leaving states undefined or incorrectly implementing transitions—an attacker can manipulate it into a deadlock or unrecoverable error state. This typically crashes the affected component or requires a full system reset to restore functionality, resulting in a denial of service. The security impact escalates when FSMs are used to enforce privilege levels or authorization checks. By driving the FSM into an unintended state, an attacker might bypass security gates, gain elevated privileges, or corrupt secure data transfers. This initial compromise can then serve as a foothold to launch further attacks, ultimately undermining the hardware's intended security guarantees.
Impact: Unexpected StateDoS: Crash, Exit, or RestartDoS: InstabilityGain Privileges or Assume Identity
Effectiveness: High
verilogverilog
default: state = 2'h0;** endcase