Improper Finite State Machines (FSMs) in Hardware Logic

Incomplete Base
Structure: Simple
Description

This vulnerability occurs when hardware logic contains flawed Finite State Machines (FSMs). Attackers can exploit these design errors to force the system into an undefined or unstable condition, potentially leading to a denial of service (DoS) or allowing privilege escalation.

Extended Description

Finite State Machines are critical for managing a system's security posture and operational flow. They often control access to sensitive data and govern secure operations. If an FSM is poorly designed—for example, by leaving states undefined or incorrectly implementing transitions—an attacker can manipulate it into a deadlock or unrecoverable error state. This typically crashes the affected component or requires a full system reset to restore functionality, resulting in a denial of service. The security impact escalates when FSMs are used to enforce privilege levels or authorization checks. By driving the FSM into an unintended state, an attacker might bypass security gates, gain elevated privileges, or corrupt secure data transfers. This initial compromise can then serve as a foothold to launch further attacks, ultimately undermining the hardware's intended security guarantees.

Common Consequences 1
Scope: AvailabilityAccess Control

Impact: Unexpected StateDoS: Crash, Exit, or RestartDoS: InstabilityGain Privileges or Assume Identity

Potential Mitigations 1
Phase: Architecture and DesignImplementation
Define all possible states and handle all unused states through default statements. Ensure that system defaults to a secure state.

Effectiveness: High

Demonstrative Examples 1

ID : DX-152

The Finite State Machine (FSM) shown in the "bad" code snippet below assigns the output ("out") based on the value of state, which is determined based on the user provided input ("user_input").

Code Example:

Bad
Verilog
verilog
The case statement does not include a default to handle the scenario when the user provides inputs of 3'h6 and 3'h7. Those inputs push the system to an undefined state and might cause a crash (denial of service) or any other unanticipated outcome. Adding a default statement to handle undefined inputs mitigates this issue. This is shown in the "Good" code snippet below. The default statement is in bold.

Code Example:

Good
Verilog
verilog

default: state = 2'h0;** endcase

References 1
FSM Anomaly Detection using Formal Analysis
Farimah Farahmandi and Prabhat Mishra
ID: REF-1060
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
System on Chip : Undetermined
Modes of Introduction
Architecture and Design
Implementation