Improper Access Control for Register Interface

Description

This vulnerability occurs when a system's hardware registers, which act as a software-to-hardware control panel, lack proper access restrictions. Malicious or flawed software can directly manipulate these registers, leading to unauthorized changes in hardware behavior.

Extended Description

In modern System-on-Chip (SoC) and embedded designs, software controls hardware peripherals—like cryptographic engines or communication modules—through memory-mapped registers. Think of these registers as a set of front-panel switches and dials for the hardware. If any software component can freely access all registers without checks, it creates a direct path for attackers to tamper with security-critical operations. This improper gatekeeping can lead to a complete breach of system confidentiality and integrity. An attacker could, for example, reconfigure a secure element to leak encryption keys, disable a firewall, or alter boot sequences. Effectively, the hardware's security is only as strong as the software's ability to protect this vital control interface from unauthorized modification.

Common Consequences 1

Scope: ConfidentialityIntegrity

Impact: Read MemoryRead Application DataModify MemoryModify Application DataGain Privileges or Assume IdentityBypass Protection MechanismUnexpected StateAlter Execution Logic

Confidentiality of hardware assets may be violated if the protected information can be read out by software through the register interface. Registers storing security state, settings, other security-critical data may be corruptible by software without correctly implemented protections.

Detection Methods 7

Manual AnalysisModerate

This is applicable in the Architecture phase before implementation started. Make sure access policy is specified for the entire memory map. Manual analysis may not ensure the implementation is correct.

Manual AnalysisModerate

Registers controlling hardware should have access control implemented. This access control may be checked manually for correct implementation. Items to check consist of how are trusted parties set, how are trusted parties verified, how are accesses verified, etc. Effectiveness of a manual analysis will vary depending upon how complicated the interface is constructed.

Simulation / EmulationModerate

Functional simulation is applicable during the Implementation Phase. Testcases must be created and executed for memory mapped registers to verify adherence to the access control policy. This method can be effective, since functional verification needs to be performed on the design, and verification for this weakness will be included. There can be difficulty covering the entire memory space during the test.

Formal VerificationHigh

Formal verification is applicable during the Implementation phase. Assertions need to be created in order to capture illegal register access scenarios and prove that they cannot occur. Formal methods are exhaustive and can be very effective, but creating the cases for large designs may be complex and difficult.

Automated AnalysisHigh

Information flow tracking can be applicable during the Implementation phase. Security sensitive data (assets) - for example, as stored in registers - is automatically tracked over time through the design to verify the data doesn't reach illegal destinations that violate the access policies for the memory map. This method can be very effective when used together with simulation and emulation, since detecting violations doesn't rely on specific scenarios or data values. This method does rely on simulation and emulation, so testcases must exist in order to use this method.

Architecture or Design ReviewModerate

Manual documentation review of the system memory map, register specification, and permissions associated with accessing security-relevant functionality exposed via memory-mapped registers.

FuzzingModerate

Perform penetration testing (either manual or semi-automated with fuzzing) to verify that access control mechanisms such as the memory protection units or on-chip bus firewall settings adequately protect critical hardware registers from software access.

Potential Mitigations 2

Phase: Architecture and Design

Design proper policies for hardware register access from software.

Phase: Implementation

Ensure that access control policies for register access are implemented in accordance with the specified design.

Demonstrative Examples 2

The register interface provides software access to hardware functionality. This functionality is an attack surface. This attack surface may be used to run untrusted code on the system through the register interface. As an example, cryptographic accelerators require a mechanism for software to select modes of operation and to provide plaintext or ciphertext data to be encrypted or decrypted as well as other functions. This functionality is commonly provided through registers.

Code Example:

Bad

Cryptographic key material stored in registers inside the cryptographic accelerator can be accessed by software.

Code Example:

Good

Key material stored in registers should never be accessible to software. Even if software can provide a key, all read-back paths to software should be disabled.

The example code is taken from the Control/Status Register (CSR) module inside the processor core of the HACK@DAC'19 buggy CVA6 SoC [REF-1340]. In RISC-V ISA [REF-1341], the CSR file contains different sets of registers with different privilege levels, e.g., user mode (U), supervisor mode (S), hypervisor mode (H), machine mode (M), and debug mode (D), with different read-write policies, read-only (RO) and read-write (RW). For example, machine mode, which is the highest privilege mode in a RISC-V system, registers should not be accessible in user, supervisor, or hypervisor modes.

Code Example:

Bad

Verilog

verilog

if ((riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl) && !(csr_addr.address==riscv::CSR_MEPC)) begin**

verilog

The vulnerable example code allows the machine exception program counter (MEPC) register to be accessed from a user mode program by excluding the MEPC from the access control check. MEPC as per the RISC-V specification can be only written or read by machine mode code. Thus, the attacker in the user mode can run code in machine mode privilege (privilege escalation).

To mitigate the issue, fix the privilege check so that it throws an Illegal Instruction Exception for user mode accesses to the MEPC register. [REF-1345]

Code Example:

Good

Verilog

verilog

if ((riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl)) begin**

verilog

Observed Examples 4

CVE-2014-2915virtualization product does not restrict access to debug and other processor registers in the hardware, allowing a crash of the host or guest OS

CVE-2021-3011virtual interrupt controller in a virtualization product allows crash of host by writing a certain invalid value to a register, which triggers a fatal error instead of returning an error code

CVE-2020-12446Driver exposes access to Model Specific Register (MSR) registers, allowing admin privileges.

CVE-2015-2150Virtualization product does not restrict access to PCI command registers, allowing host crash from the guest.

References 3

Hackatdac19 csr_regfile.sv

2019

https://github.com/HACK-EVENT/hackatdac19/blob/619e9fb0ef32ee1e01ad76b8732a156572c65700/src/csr_regfile.sv#L854:L857(2023-06-21)

ID: REF-1340

The RISC-V Instruction Set Manual

Andrew Waterman, Yunsup Lee, Rimas Avižienis, David Patterson, and Krste Asanović

04-11-2016

https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.1.pdf(2023-06-21)

ID: REF-1341

csr_regfile.sv

Florian Zaruba, Michael Schaffner, and Andreas Traber

2019

https://github.com/openhwgroup/cva6/blob/7951802a0147aedb21e8f2f6dc1e1e9c4ee857a2/src/csr_regfile.sv#L868:L871(2023-06-21)

ID: REF-1345