Uninitialized Value on Reset for Registers Holding Security Settings

Incomplete Base
Structure: Simple
Description

Security-critical hardware registers start with random, unpredictable values when a device powers on or resets, creating an immediate vulnerability window before software can initialize them.

Extended Description

When a hardware device boots or comes out of reset, the registers controlling security features (like memory protection or access permissions) don't automatically set themselves to a safe state. Instead, they contain whatever random data was left in the physical circuitry, which means the device's security posture is completely undefined and unreliable at startup. This creates a dangerous gap between power-on and when the device's firmware or operating system runs its initialization code. During this window, an attacker could exploit the unconfigured security settings to bypass protections, gain unauthorized access, or manipulate the system before it has a chance to secure itself. The fix requires explicitly writing known, secure values to all security-critical registers as the very first operation after reset.

Common Consequences 1
Scope: Access ControlAuthenticationAuthorization

Impact: Varies by Context

Potential Mitigations 2
Phase: Implementation
Design checks should be performed to identify any uninitialized flip-flops used for security-critical functions.
Phase: Architecture and Design
All registers holding security-critical information should be set to a specific value on reset.
Demonstrative Examples 1
Shown below is a positive clock edge triggered flip-flop used to implement a lock bit for test and debug interface. When the circuit is first brought out of reset, the state of the flip-flop will be unknown until the enable input and D-input signals update the flip-flop state. In this example, an attacker can reset the device until the test and debug interface is unlocked and access the test interface until the lock signal is driven to a known state by the logic.

Code Example:

Bad
Verilog

always @(posedge clk) begin

verilog
The flip-flop can be set to a known value (0 or 1) on reset, but requires that the logic explicitly update the output of the flip-flop if the reset signal is active.

Code Example:

Good
Verilog

always @(posedge clk) begin

verilog
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Implementation
Related Weaknesses
Notes
MaintenanceThis entry is still under development and will continue to see updates and content improvements.