logo

Hardware Child Block Incorrectly Connected to Parent System

Incomplete Base
Structure: Simple
Description

This vulnerability occurs when a hardware component (IP block) is wired incorrectly to the main system, creating hidden security flaws even if basic functions appear to work.

Extended Description

For a system-on-chip (SoC) to operate securely, its internal hardware blocks must communicate with the parent system using the correct control and data signals. An incorrect connection—like linking a reset pin to the wrong system controller—can bypass critical security boundaries. While the device might still boot and run, this miswiring opens a backdoor that attackers can exploit to tamper with sensitive data or operations. Consider a block designed to only clear its data during a full system power cycle. If its reset line is mistakenly connected to a software-controlled debug reset, a privileged process or an attacker gaining software access could trigger an unauthorized reset. This violates the hardware's data integrity guarantees, potentially leaking secrets or corrupting secure state, all while the system seems to function normally from a user's perspective.
Common Consequences 1
Scope: ConfidentialityIntegrityAvailability

Impact: Varies by Context
Potential Mitigations 1
Phase: Testing
System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks.
Demonstrative Examples 2
Many SoCs use hardware to partition system resources between trusted and un-trusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.

Code Example:

Bad
Verilog

// IP definition module tz_peripheral(clk, reset, data_in, data_in_security_level, ...);

verilog
In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded.

Code Example:

Good
Verilog

// Instantiation of IP in a parent system module soc(...)

verilog
Here is a code snippet from the Ariane core module in the HACK@DAC'21 Openpiton SoC [REF-1362]. To ensure full functional correctness, developers connect the ports with names. However, in some cases developers forget to connect some of these ports to the desired signals in the parent module. These mistakes by developers can lead to incorrect functional behavior or, in some cases, introduce security vulnerabilities.

Code Example:

Bad
Verilog

... csr_regfile #(

verilog

.irq_i(),**

verilog

...

In the above example from HACK@DAC'21, since interrupt signals are not properly connected, the CSR module will fail to send notifications in the event of interrupts. Consequently, critical information in CSR registers that should be flushed or modified in response to an interrupt won't be updated. These vulnerabilities can potentially result in information leakage across various privilege levels.
To address the aforementioned vulnerability, developers must follow a two-step approach. First, they should ensure that all module signals are properly connected. This can often be facilitated using automated tools, and many simulators and sanitizer tools issue warnings when a signal remains unconnected or floats. Second, it is imperative to validate that the signals connected to a module align with the specifications. In the provided example, the developer should establish the correct connection of interrupt signals from the parent module (Ariane core) to the child module (csr_regfile) [REF-1363].

Code Example:

Good
Verilog

... csr_regfile #(

verilog

.irq_i (irq_i),**

verilog

...
References 2
ariane.sv
2021
https://github.com/HACK-EVENT/hackatdac21/blob/b9ecdf6068445d76d6bee692d163fededf7a9d9b/piton/design/chip/tile/ariane/src/ariane.sv#L539:L540(2023-07-15)
ID: REF-1362
Fix CWE-1276
2021
https://github.com/HACK-EVENT/hackatdac21/blob/9a796ee83e21f59476d4b0a68ec3d8e8d5148214/piton/design/chip/tile/ariane/src/ariane.sv#L539:L540(2023-09-01)
ID: REF-1363
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Implementation
Related Weaknesses
ChildOf: Improper Access Control (CWE-284)