logo

Hardware Logic Contains Race Conditions

Draft Base
Structure: Simple
Description

A hardware race condition occurs when security-critical logic circuits receive signals at slightly different times, creating temporary glitches that can bypass system protections.

Extended Description

In hardware design, race conditions happen when signals from the same source take different paths through logic gates and arrive at slightly different times. This timing mismatch can cause a gate's output to flicker into an incorrect state—a glitch—before settling correctly. These glitches, though often brief, create a window where the hardware operates in an unintended state. When these timing errors occur in security-sensitive circuits like access control modules or cryptographic state machines, they become critical vulnerabilities. Attackers can deliberately trigger or amplify these glitches to bypass authentication, escalate privileges, or leak protected data, effectively undermining the hardware's security guarantees.
Common Consequences 1
Scope: Access Control

Impact: Bypass Protection MechanismGain Privileges or Assume IdentityAlter Execution Logic
Potential Mitigations 2
Phase: Architecture and Design
Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.
Phase: Implementation
Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.
Demonstrative Examples 2
The code below shows a 2x1 multiplexor using logic gates. Though the code shown below results in the minimum gate solution, it is disjoint and causes glitches.

Code Example:

Bad
Verilog

// 2x1 Multiplexor using logic-gates

module glitchEx(

verilog
The buggy line of code, commented above, results in signal 'z' periodically changing to an unwanted state. Thus, any logic that references signal 'z' may access it at a time when it is in this unwanted state. This line should be replaced with the line shown below in the Good Code Snippet which results in signal 'z' remaining in a continuous, known, state. Reference for the above code, along with waveforms for simulation can be found in the references below.

Code Example:

Good
Verilog

assign z <= and_out1 or and_out2 or (in0 and in1);

This line of code removes the glitch in signal z.
The example code is taken from the DMA (Direct Memory Access) module of the buggy OpenPiton SoC of HACK@DAC'21. The DMA contains a finite-state machine (FSM) for accessing the permissions using the physical memory protection (PMP) unit. PMP provides secure regions of physical memory against unauthorized access. It allows an operating system or a hypervisor to define a series of physical memory regions and then set permissions for those regions, such as read, write, and execute permissions. When a user tries to access a protected memory area (e.g., through DMA), PMP checks the access of a PMP address (e.g., pmpaddr_i) against its configuration (pmpcfg_i). If the access violates the defined permissions (e.g., CTRL_ABORT), the PMP can trigger a fault or an interrupt. This access check is implemented in the pmp parametrized module in the below code snippet. The below code assumes that the state of the pmpaddr_i and pmpcfg_i signals will not change during the different DMA states (i.e., CTRL_IDLE to CTRL_DONE) while processing a DMA request (via dma_ctrl_reg). The DMA state machine is implemented using a case statement (not shown in the code snippet).

Code Example:

Bad
Verilog

module dma # (...)(...); ...

verilog

pmpaddr_i** ), .conf_i ( pmpcfg_i ), .allow_o ( pmp_data_allow ) ); endmodule

However, the above code [REF-1394] allows the values of pmpaddr_i and pmpcfg_i to be changed through DMA's input ports. This causes a race condition and will enable attackers to access sensitive addresses that the configuration is not associated with. Attackers can initialize the DMA access process (CTRL_IDLE) using pmpcfg_i for a non-privileged PMP address (pmpaddr_i). Then during the loading state (CTRL_LOAD), attackers can replace the non-privileged address in pmpaddr_i with a privileged address without the requisite authorized access configuration. To fix this issue (see [REF-1395]), the value of the pmpaddr_i and pmpcfg_i signals should be stored in local registers (pmpaddr_reg and pmpcfg_reg at the start of the DMA access process and the pmp module should reference those registers instead of the signals directly. The values of the registers can only be updated at the start (CTRL_IDLE) or the end (CTRL_DONE) of the DMA access process, which prevents attackers from changing the PMP address in the middle of the DMA access process.

Code Example:

Good
Verilog

module dma # (...)(...); ...

verilog

reg [7:0] [16-1:0] pmpcfg_reg;**

verilog
verilog

pmpaddr_reg <= pmpaddr_i;**

verilog
verilog
References 4
FPGA designs with Verilog (section 7.4 Glitches)
Meher Krishna Patel
https://verilogguide.readthedocs.io/en/latest/verilog/fsm.html
ID: REF-1115
Non-Blocking Assignments in Verilog Synthesis, Coding Styles that Kill!
Clifford E. Cummings
2000
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf
ID: REF-1116
dma.sv
2021
https://github.com/HACK-EVENT/hackatdac21/blob/main/piton/design/chip/tile/ariane/src/dma/dma.sv(2024-02-09)
ID: REF-1394
Fix for dma.sv
2021
https://github.com/HACK-EVENT/hackatdac21/blob/cwe_1298_in_dma/piton/design/chip/tile/ariane/src/dma/dma.sv(2024-02-09)
ID: REF-1395
Applicable Platforms
Languages:
Verilog : UndeterminedVHDL : Undetermined
Technologies:
System on Chip : Undetermined
Modes of Introduction
Architecture and Design
Implementation
Related Attack Patterns
Related Weaknesses
ChildOf: Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition') (CWE-362)