Hardware Allows Activation of Test or Debug Logic at Runtime

Draft Base
Structure: Simple
Description

This vulnerability occurs when hardware includes test or debug features that remain accessible during normal operation. An attacker can activate these features at runtime to alter the hardware's state, bypass security controls, and potentially leak or manipulate sensitive data.

Extended Description

Attackers exploit this weakness by accessing hardware test modes—like debug interfaces or error injection circuits—that were intended only for development or manufacturing. Once activated, these features can grant unauthorized read/write access to system memory, registers, or buses, allowing an adversary to directly modify the device's behavior or extract secrets. For example, an accessible debug mode might let an attacker intercept or alter data on a communication bus, leading to malicious message injection. Similarly, runtime error injection could corrupt cryptographic operations or expose keys. These capabilities effectively create backdoors that compromise both system integrity and data confidentiality.

Common Consequences 1
Scope: ConfidentialityIntegrityAvailability

Impact: Modify MemoryRead MemoryDoS: Crash, Exit, or RestartDoS: InstabilityDoS: Resource Consumption (CPU)DoS: Resource Consumption (Memory)DoS: Resource Consumption (Other)Execute Unauthorized Code or CommandsGain Privileges or Assume IdentityBypass Protection MechanismAlter Execution LogicQuality DegradationUnexpected StateReduce PerformanceReduce Reliability

Potential Mitigations 3
Phase: Architecture and Design
Insert restrictions on when the hardware's test or debug features can be activated. For example, during normal operating modes, the hardware's privileged modes that allow access to such features cannot be activated. Configuring the hardware to only enter a test or debug mode within a window of opportunity such as during boot or configuration stage. The result is disablement of such test/debug features and associated modes during normal runtime operations.
Phase: Implementation
Insert restrictions on when the hardware's test or debug features can be activated. For example, during normal operating modes, the hardware's privileged modes that allow access to such features cannot be activated. Configuring the hardware to only enter a test or debug mode within a window of opportunity such as during boot or configuration stage. The result is disablement of such test/debug features and associated modes during normal runtime operations.
Phase: Integration
Insert restrictions on when the hardware's test or debug features can be activated. For example, during normal operating modes, the hardware's privileged modes that allow access to such features cannot be activated. Configuring the hardware to only enter a test or debug mode within a window of opportunity such as during boot or configuration stage. The result is disablement of such test/debug features and associated modes during normal runtime operations.
Observed Examples 2
CVE-2021-33150Hardware processor allows activation of test or debug logic at runtime.
CVE-2021-0146Processor allows the activation of test or debug logic at runtime, allowing escalation of privileges
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Architecture and Design
Implementation
Integration
Related Attack Patterns
Related Weaknesses