Improper Setting of Bus Controlling Capability in Fabric End-point

Incomplete Base
Structure: Simple
Description

This vulnerability occurs when a hardware fabric endpoint is incorrectly configured to grant bus controller privileges to a device that should only respond to requests. This allows an unauthorized device to initiate and control data transactions across the system bus.

Extended Description

Many modern system-on-chip (SoC) designs use reusable fabric endpoints with a configurable control bit. This bit determines whether a connected IP block (like a peripheral) can act only as a responder to requests, or if it can also act as a controller, initiating transactions to access other system components. While this flexibility aids hardware reuse, it introduces a critical security boundary. If this control bit is enabled by default in the hardware design, or if system firmware or software incorrectly sets it during operation, a peripheral intended to be passive gains unauthorized control over the system fabric. This compromised device can then read from or write to sensitive memory regions or other peripherals, leading to data exposure, privilege escalation, or a complete system takeover.

Common Consequences 1
Scope: Access Control

Impact: Modify MemoryRead MemoryBypass Protection Mechanism

Potential Mitigations 3
Phase: Architecture and Design
For responder devices, the register bit in the fabric end-point that enables the bus controlling capability must be set to 0 by default. This bit should not be set during secure-boot flows. Also, writes to this register must be access-protected to prevent malicious modifications to obtain bus-controlling capability.
Phase: Implementation
For responder devices, the register bit in the fabric end-point that enables the bus controlling capability must be set to 0 by default. This bit should not be set during secure-boot flows. Also, writes to this register must be access-protected to prevent malicious modifications to obtain bus-controlling capability.
Phase: System Configuration
For responder devices, the register bit in the fabric end-point that enables the bus controlling capability must be set to 0 by default. This bit should not be set during secure-boot flows. Also, writes to this register must be access-protected to prevent malicious modifications to obtain bus-controlling capability.
Demonstrative Examples 1
A typical, phone platform consists of the main, compute core or CPU, a DRAM-memory chip, an audio codec, a baseband modem, a power-management-integrated circuit ("PMIC"), a connectivity (WiFi and Bluetooth) modem, and several other analog/RF components. The main CPU is the only component that can control transactions, and all the other components are responder-only devices. All the components implement a PCIe end-point to interface with the rest of the platform. The responder devices should have the bus-control-enable bit in the PCIe-end-point register set to 0 in hardware to prevent the devices from controlling transactions to the CPU or other peripherals.
The audio-codec chip does not have the bus-controller-enable-register bit hardcoded to 0. There is no platform-firmware flow to verify that the bus-controller-enable bit is set to 0 in all responders.
Audio codec can now master transactions to the CPU and other platform components. Potentially, it can modify assets in other platform components to subvert system security.
Platform firmware includes a flow to check the configuration of bus-controller-enable bit in all responder devices. If this register bit is set on any of the responders, platform firmware sets it to 0. Ideally, the default value of this register bit should be hardcoded to 0 in RTL. It should also have access control to prevent untrusted entities from setting this bit to become bus controllers.
References 2
Bypassing IOMMU Protection against I/O Attacks
Benoit Morgan, Eric Alata, Vincent Nicomette, Mohamed Kaaniche
2016
ID: REF-1135
Exploitation from malicious PCI Express peripherals
Colin L. Rothwell
2019
ID: REF-1136
Applicable Platforms
Languages:
Not Language-Specific : Undetermined
Technologies:
Not Technology-Specific : Undetermined
Modes of Introduction
Architecture and Design
Implementation
System Configuration
Related Weaknesses