Improper Access Control in Fabric Bridge

Draft Base

Structure: Simple

Description

This vulnerability occurs when a hardware fabric bridge, which connects different IP blocks on a chip, fails to properly verify access permissions for transactions passing through it. The bridge forwards requests without checking the master's privilege level or the hardware identity, effectively bypassing critical security controls.

Extended Description

In modern System-on-Chip (SoC) designs, various Intellectual Property (IP) blocks communicate through a central interconnect bus using different protocols like AHB or OCP. A fabric bridge acts as a translator and router between these blocks. For system security to hold, every transaction's access-control privileges—such as user vs. supervisor mode or secure vs. non-secure identity—must be preserved and enforced as it crosses this bridge. If the bridge is connected to a non-secure fabric or simply forwards transactions without validation, it creates a critical gap. An unauthorized master IP could access restricted slave IPs, or a slave could spoof its identity, leading to privilege escalation, data exposure, or unauthorized control within the chip. Ensuring the bridge actively checks and enforces these controls is essential for maintaining the SoC's security boundaries.

Common Consequences 1

Scope: ConfidentialityIntegrityAccess ControlAvailability

Impact: DoS: Crash, Exit, or RestartBypass Protection MechanismRead MemoryModify Memory

Detection Methods 2

Simulation / EmulationHigh

RTL simulation to ensure that bridge-access controls are implemented properly.

Formal VerificationHigh

Formal verification of bridge RTL to ensure that access control cannot be bypassed.

Potential Mitigations 2

Phase: Architecture and Design

Ensure that the design includes provisions for access-control checks in the bridge for both upstream and downstream transactions.

Phase: Implementation

Implement access-control checks in the bridge for both upstream and downstream transactions.

Demonstrative Examples 2

This example is from CVE-2019-6260 [REF-1138]. The iLPC2AHB bridge connects a CPU (with multiple, privilege levels, such as user, super user, debug, etc.) over AHB interface to an LPC bus. Several peripherals are connected to the LPC bus. The bridge is expected to check the privilege level of the transactions initiated in the core before forwarding them to the peripherals on the LPC bus.

The bridge does not implement the checks and allows reads and writes from all privilege levels.

To address this, designers should implement hardware-based checks that are either hardcoded to block untrusted agents from accessing secure peripherals or implement firmware flows that configure the bridge to block untrusted agents from making arbitrary reads or writes.

The example code below is taken from the AES and core local interrupt (CLINT) peripherals of the HACK@DAC'21 buggy OpenPiton SoC. The access to all the peripherals for a given privilege level of the processor is controlled by an access control module in the SoC. This ensures that malicious users with insufficient privileges do not get access to sensitive data, such as the AES keys used by the operating system to encrypt and decrypt information. The security of the entire system will be compromised if the access controls are incorrectly enforced. The access controls are enforced through the interconnect-bus fabrics, where access requests with insufficient access control permissions will be rejected.

Code Example:

Bad

Verilog

... module aes0_wrapper #(...)(...); ...

verilog

.en_o ( en_acct ),** ... ..);

assign en = en_acct && acct_ctrl_i;** ... endmodule ... module clint #(...)(...); ...

verilog

.en_o ( en ),** ... ); ... endmodule

The previous code snippet [REF-1382] illustrates an instance of a vulnerable implementation of access control for the CLINT peripheral (see module clint). It also shows a correct implementation of access control for the AES peripheral (see module aes0_wrapper) [REF-1381]. An enable signal (en_o) from the fabric's AXI interface (present in both modules) is used to determine if an access request is made to the peripheral. In the case of the AES peripheral, this en_o signal is first received in a temporary signal en_acct. Then, the access request is enabled (by asserting the en signal) only if the request has sufficient access permissions (i.e., acct_ctrl_i signal should be enabled). However, in the case of the CLINT peripheral, the enable signal, en_o, from the AXI interface, is directly used to enable accesses. As a result, users with insufficient access permissions also get full access to the CLINT peripheral.

To fix this, enable access requests to CLINT [REF-1383] only if the user has sufficient access as indicated by the acct_ctrl_i signal in the boolean && with en_acct.

Code Example:

Good

Verilog

module clint #(... ) ( ...

input logic acct_ctrl_i,** ... );

verilog

, en_acct** ; ...

verilog

en_acct** ), ...

verilog

assign en = en_acct && acct_ctrl_i;** ... endmodule

Observed Examples 1

CVE-2019-6260Baseboard Management Controller (BMC) device implements Advanced High-performance Bus (AHB) bridges that do not require authentication for arbitrary read and write access to the BMC's physical address space from the host, and possibly the network [REF-1138].

References 4

CVE-2019-6260: Gaining control of BMC from the host processor

Stewart Smith

2019

https://www.flamingspork.com/blog/2019/01/23/cve-2019-6260:-gaining-control-of-bmc-from-the-host-processor/(2025-07-29)

ID: REF-1138

aes0_wrapper.sv lines 72 - 78

2021

https://github.com/HACK-EVENT/hackatdac21/blob/b9ecdf6068445d76d6bee692d163fededf7a9d9b/piton/design/chip/tile/ariane/src/aes0/aes0_wrapper.sv#L72-L78(2024-01-16)

ID: REF-1381

clint.sv line 71

2021