This weakness occurs when a system fails to properly set up a resource during its creation, leaving it in an unstable, incorrect, or insecure state when used later.
In software, this often happens due to reliance on implicit or default initialization. For instance, in C, stack memory isn't automatically cleared, and many scripting languages assign a default null or zero value to uninitialized variables. This can lead to critical security flaws if the resource controls access, like an authentication flag, or holds sensitive configuration data. In hardware, similar issues arise from incorrect reset values, misconfigured security fuses, or physical defects. Even if fuses are programmed correctly, broken lines or interfering hardware can corrupt the value. This incorrect initialization during boot or reset can compromise the entire device's security posture from the start.
Impact: Read MemoryRead Application DataUnexpected State
Impact: Gain Privileges or Assume Identity
Impact: Varies by Context
The technical impact can vary widely based on how the resource is used in the product, and whether its contents affect security decisions.
// Parameterized Register module example // Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable// module register_example #( parameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits parameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register computed from Width. Sets all bits to 1s except bit 0 (Secure _mode) ) ( input [REGISTER_WIDTH-1:0] Data_in, input Clk, input resetn, input write, output reg [REGISTER_WIDTH-1:0] Data_out );
reg Secure_mode;
always @(posedge Clk or negedge resetn)
verilogregister_example #(
verilog// $user and $pass automatically set from POST request* if (login_user($user,$pass)) { ``` $authorized = true; }
phpphp
...*
module acct_wrapper #( ...
verilog
acct_mem[j] <= 32'hffffffff;** end end ...
module acct_wrapper #( ...
verilog
acct_mem[j] <= 32'h00000000;** end end ...