CWE-1221 Base Incomplet

Incorrect Register Defaults or Module Parameters

This vulnerability occurs when hardware description language (HDL) code sets insecure default values for hardware registers or configurable module parameters. These hardcoded values leave the…

Définition

What is CWE-1221?

This vulnerability occurs when hardware description language (HDL) code sets insecure default values for hardware registers or configurable module parameters. These hardcoded values leave the hardware in an unsafe state after a reset, creating a permanent security weakness that software cannot patch.

Hardware designs use registers to store programmable settings and controls, which must be initialized to secure default values upon reset. These defaults, along with configurable parameters that define how a hardware module behaves, are hardcoded directly into the HDL. If these values are set insecurely, the hardware boots into a vulnerable state that untrusted software could immediately exploit. Because these defaults and parameters are baked into the silicon during manufacturing, they cannot be fixed with a software or firmware update. This makes such flaws especially critical and expensive to correct later. Given the large number of configurable settings in modern designs, automated tooling is essential to scan for and flag security-sensitive parameters, ensuring they are properly configured from the start.

Impact réel

Real-world CVEs caused by CWE-1221

Aucune référence CVE publique n'est liée à ce CWE dans le catalogue MITRE pour le moment.

Comment les attaquants l'exploitent

Parcours de l'attaquant étape par étape

1
Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.
2
These example instantiations show how, in a hardware design, it would be possible to instantiate the register module with insecure defaults and parameters.
3
In the example design, both registers will be software writable since Secure_mode is defined as zero.
4
The example code is taken from the fuse memory inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1356]. Fuse memory can be used to store key hashes, password hashes, and configuration information. For example, the password hashes of JTAG and HMAC are stored in the fuse memory in the OpenPiton design.
5
During the firmware setup phase, data in the Fuse memory are transferred into the registers of the corresponding SoC peripherals for initialization. However, if the offset to access the password hash is set incorrectly, programs cannot access the correct password hash from the fuse memory, breaking the functionalities of the peripherals and even exposing sensitive information through other peripherals.

Exemple de code vulnérable

Vulnerable Verilog

Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.

Vulnérable Verilog

// Parameterized Register module example 
 // Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable// 
 module register_example 
 #( 
 parameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits 
 parameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register computed from Width. Sets all bits to 1s except bit 0 (Secure _mode) 
 ) 
 ( 
 input [REGISTER_WIDTH-1:0] Data_in, 
 input Clk, 
 input resetn, 
 input write, 
 output reg [REGISTER_WIDTH-1:0] Data_out 
 ); 

 reg Secure_mode; 

 always @(posedge Clk or negedge resetn) 

```
   if (~resetn) 
   begin 
  	 Data_out <= REGISTER_DEFAULT; // Register content set to Default at reset 
  	 Secure_mode <= REGISTER_DEFAULT[0]; // Register Secure_mode set at reset 
   end 
   else if (write & ~Secure_mode) 
   begin 
  	 Data_out <= Data_in; 
   end 
 endmodule 
 module register_top 
 ( 
 input Clk, 
 input resetn, 
 input write, 
 input [31:0] Data_in, 
 output reg [31:0] Secure_reg, 
 output reg [31:0] Insecure_reg 
 ); 
 register_example #( 
   .REGISTER_WIDTH (32), 
   .REGISTER_DEFAULT (1224) // Incorrect Default value used bit 0 is 0. 
 ) Insecure_Device_ID_1 ( 
   .Data_in (Data_in), 
   .Data_out (Secure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 ); 
 register_example #(
   .REGISTER_WIDTH (32) // Default not defined 2^32-2 value will be used as default. 
 ) Insecure_Device_ID_2 ( 
   .Data_in (Data_in), 
   .Data_out (Insecure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 ); 
 endmodule

Exemple de code sécurisé

Secure Verilog

In the example design, both registers will be software writable since Secure_mode is defined as zero.

Sécurisé Verilog

register_example #( 

```
   .REGISTER_WIDTH (32), 
   .REGISTER_DEFAULT (1225) // Correct default value set, to enable Secure_mode 
 ) Secure_Device_ID_example ( 
   .Data_in (Data_in), 
   .Data_out (Secure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 );

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Liste de contrôle de prévention

How to prevent CWE-1221

Architecture and Design During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings.
Implementation The default values of these security sensitive settings need to be defined as part of the design review phase.
Testing Testing phase should use automated tools to test that values are configured per design specifications.

Signaux de détection

How to detect CWE-1221

SAST High

Exécuter une analyse statique (SAST) sur le code source à la recherche du motif non sécurisé dans le flux de données.

DAST Moderate

Exécuter des tests de sécurité applicative dynamique (DAST) contre le point de terminaison en ligne.

Runtime Moderate

Surveiller les journaux runtime pour détecter des traces d'exception inhabituelles, des entrées malformées ou des tentatives de contournement d'autorisation.

Code review Moderate

Revue de code : signaler tout nouveau code qui traite les entrées de cette surface sans utiliser les helpers du framework validés.

Correction automatique Plexicus

Plexicus détecte automatiquement CWE-1221 et ouvre une PR de correction en moins de 60 secondes.

Codex Remedium analyse chaque commit, identifie cette faiblesse précise et livre une pull request prête à être relue avec le correctif. Pas de tickets. Pas de transferts.

Obtenir une démo Essayer Plexicus gratuitement

Questions fréquentes

Frequently asked questions

Qu'est-ce que CWE-1221 ?

Quelle est la gravité de CWE-1221 ?

MITRE n'a pas publié de note de probabilité d'exploitation pour cette faiblesse. Traitez-la comme un impact moyen jusqu'à ce que votre modèle de menace prouve le contraire.

Quels langages ou plateformes sont affectés par CWE-1221 ?

MITRE lists the following affected platforms: Verilog, VHDL, Not Technology-Specific.

Comment puis-je prévenir CWE-1221 ?

During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings. The default values of these security sensitive settings need to be defined as part of the design review phase.

Comment Plexicus détecte et corrige CWE-1221 ?

Le moteur SAST de Plexicus reconnaît la signature de flux de données de CWE-1221 à chaque commit. Lorsqu'une correspondance est trouvée, notre agent Codex Remedium ouvre une PR de correction avec le code corrigé, les tests et un résumé d'une ligne pour le relecteur.

Où puis-je en savoir plus sur CWE-1221 ?

MITRE publie la définition canonique à https://cwe.mitre.org/data/definitions/1221.html. Vous pouvez également consulter la documentation OWASP et NIST pour des conseils adjacents.

Faiblesses associées

Weaknesses related to CWE-1221

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