CWE-1224 Base Incomplet

Improper Restriction of Write-Once Bit Fields

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Définition

What is CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.
Hardware designs use special write-once or 'sticky' bit fields in control registers to lock critical settings. These are intended to be configured only once—typically during initial boot by trusted firmware—and then become permanently read-only. This mechanism is a fundamental security feature that prevents runtime software or malware from altering secure hardware configurations, such as memory protection or debug access controls. When this restriction fails, software can repeatedly overwrite these bits. A common implementation flaw is creating 'write-1-once' logic instead of true 'write-once' protection. In this flawed scenario, a bit might only become locked after being set to '1,' leaving it vulnerable if set to '0' first or allowing toggling between values. This exposes the hardware to privilege escalation, system compromise, or bypass of critical security boundaries.
Impact réel

Real-world CVEs caused by CWE-1224

Aucune référence CVE publique n'est liée à ce CWE dans le catalogue MITRE pour le moment.

Comment les attaquants l'exploitent

Parcours de l'attaquant étape par étape

  1. 1

    Identifier un chemin de code qui traite des entrées non fiables sans validation.

  2. 2

    Élaborer une charge utile qui exploite le comportement non sécurisé — injection, traversal, débordement ou abus de logique.

  3. 3

    Délivrer la charge utile via une requête normale et observer la réaction de l'application.

  4. 4

    Itérer jusqu'à ce que la réponse divulgue des données, exécute le code de l'attaquant ou élève les privilèges.

Exemple de code vulnérable

Vulnerable Verilog

Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value. This implementation can be for a register that is defined by specification to be a write-once register, since the write_once_status field gets written by input data bit 0 on first write.

Vulnérable Verilog 
module register_write_once_example
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn,
 input write,
 output reg [15:0] Data_out 
 );

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn)

```
   if (~ip_resetn)
   begin
  	 Data_out <= 16'h0000;
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status)
   begin
  	 Data_out <= Data_in & 16'hFFFE;
  	 Write_once_status <= Data_in[0]; // Input bit 0 sets Write_once_status
   end
   else if (~write)
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule
Exemple de code sécurisé

Secure Verilog

The above example only locks further writes if write_once_status bit is written to one. So it acts as write_1-Once instead of the write-once attribute.

Sécurisé Verilog 
module register_write_once_example 
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn, 
 input write, 
 output reg [15:0] Data_out 
 ); 

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn) 

```
   if (~ip_resetn) 
   begin 
  	 Data_out <= 16'h0000; 
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status) 
   begin 
  	 Data_out <= Data_in & 16'hFFFE; 
  	 Write_once_status <= 1'b1; // Write once status set on first write, independent of input 
   end 
   else if (~write) 
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Liste de contrôle de prévention

How to prevent CWE-1224

  • Architecture and Design During hardware design all register write-once or sticky fields must be evaluated for proper configuration.
  • Testing The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.
Signaux de détection

How to detect CWE-1224

SAST High

Exécuter une analyse statique (SAST) sur le code source à la recherche du motif non sécurisé dans le flux de données.

DAST Moderate

Exécuter des tests de sécurité applicative dynamique (DAST) contre le point de terminaison en ligne.

Runtime Moderate

Surveiller les journaux runtime pour détecter des traces d'exception inhabituelles, des entrées malformées ou des tentatives de contournement d'autorisation.

Code review Moderate

Revue de code : signaler tout nouveau code qui traite les entrées de cette surface sans utiliser les helpers du framework validés.

Correction automatique Plexicus

Plexicus détecte automatiquement CWE-1224 et ouvre une PR de correction en moins de 60 secondes.

Codex Remedium analyse chaque commit, identifie cette faiblesse précise et livre une pull request prête à être relue avec le correctif. Pas de tickets. Pas de transferts.

Obtenir une démo Essayer Plexicus gratuitement
Questions fréquentes

Frequently asked questions

Qu'est-ce que CWE-1224 ?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Quelle est la gravité de CWE-1224 ?

MITRE n'a pas publié de note de probabilité d'exploitation pour cette faiblesse. Traitez-la comme un impact moyen jusqu'à ce que votre modèle de menace prouve le contraire.

Quels langages ou plateformes sont affectés par CWE-1224 ?

MITRE lists the following affected platforms: Verilog, VHDL, System on Chip.

Comment puis-je prévenir CWE-1224 ?

During hardware design all register write-once or sticky fields must be evaluated for proper configuration. The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

Comment Plexicus détecte et corrige CWE-1224 ?

Le moteur SAST de Plexicus reconnaît la signature de flux de données de CWE-1224 à chaque commit. Lorsqu'une correspondance est trouvée, notre agent Codex Remedium ouvre une PR de correction avec le code corrigé, les tests et un résumé d'une ligne pour le relecteur.

Où puis-je en savoir plus sur CWE-1224 ?

MITRE publie la définition canonique à https://cwe.mitre.org/data/definitions/1224.html. Vous pouvez également consulter la documentation OWASP et NIST pour des conseils adjacents.

Faiblesses associées

Weaknesses related to CWE-1224

CWE-284 Parent

Improper Access Control

The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.

CWE-1191 Frère

On-Chip Debug and Test Interface With Improper Access Control

This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…

CWE-1220 Frère

Insufficient Granularity of Access Control

This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…

CWE-1231 Frère

Improper Prevention of Lock Bit Modification

This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to…

CWE-1233 Frère

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to…

CWE-1252 Frère

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…

CWE-1257 Frère

Improper Access Control Applied to Mirrored or Aliased Memory Regions

This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to…

CWE-1259 Frère

Improper Restriction of Security Token Assignment

This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…

CWE-1260 Frère

Improper Handling of Overlap Between Protected Memory Ranges

This vulnerability occurs when a system incorrectly allows different memory protection ranges to overlap. This flaw can let attackers…

Ressources

Further reading

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