CWE-1221 Base Incompleto

Incorrect Register Defaults or Module Parameters

This vulnerability occurs when hardware description language (HDL) code sets insecure default values for hardware registers or configurable module parameters. These hardcoded values leave the…

Definição

What is CWE-1221?

This vulnerability occurs when hardware description language (HDL) code sets insecure default values for hardware registers or configurable module parameters. These hardcoded values leave the hardware in an unsafe state after a reset, creating a permanent security weakness that software cannot patch.

Hardware designs use registers to store programmable settings and controls, which must be initialized to secure default values upon reset. These defaults, along with configurable parameters that define how a hardware module behaves, are hardcoded directly into the HDL. If these values are set insecurely, the hardware boots into a vulnerable state that untrusted software could immediately exploit. Because these defaults and parameters are baked into the silicon during manufacturing, they cannot be fixed with a software or firmware update. This makes such flaws especially critical and expensive to correct later. Given the large number of configurable settings in modern designs, automated tooling is essential to scan for and flag security-sensitive parameters, ensuring they are properly configured from the start.

Impacto no mundo real

Real-world CVEs caused by CWE-1221

Ainda não há referências CVE públicas associadas a este CWE no catálogo da MITRE.

Como os atacantes a exploram

Trajeto do atacante passo a passo

1
Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.
2
These example instantiations show how, in a hardware design, it would be possible to instantiate the register module with insecure defaults and parameters.
3
In the example design, both registers will be software writable since Secure_mode is defined as zero.
4
The example code is taken from the fuse memory inside the buggy OpenPiton SoC of HACK@DAC'21 [REF-1356]. Fuse memory can be used to store key hashes, password hashes, and configuration information. For example, the password hashes of JTAG and HMAC are stored in the fuse memory in the OpenPiton design.
5
During the firmware setup phase, data in the Fuse memory are transferred into the registers of the corresponding SoC peripherals for initialization. However, if the offset to access the password hash is set incorrectly, programs cannot access the correct password hash from the fuse memory, breaking the functionalities of the peripherals and even exposing sensitive information through other peripherals.

Exemplo de código vulnerável

Vulnerable Verilog

Consider example design module system verilog code shown below. The register_example module is an example parameterized module that defines two parameters, REGISTER_WIDTH and REGISTER_DEFAULT. Register_example module defines a Secure_mode setting, which when set makes the register content read-only and not modifiable by software writes. register_top module instantiates two registers, Insecure_Device_ID_1 and Insecure_Device_ID_2. Generally, registers containing device identifier values are required to be read only to prevent any possibility of software modifying these values.

Vulnerável Verilog

// Parameterized Register module example 
 // Secure_mode : REGISTER_DEFAULT[0] : When set to 1 register is read only and not writable// 
 module register_example 
 #( 
 parameter REGISTER_WIDTH = 8, // Parameter defines width of register, default 8 bits 
 parameter [REGISTER_WIDTH-1:0] REGISTER_DEFAULT = 2**REGISTER_WIDTH -2 // Default value of register computed from Width. Sets all bits to 1s except bit 0 (Secure _mode) 
 ) 
 ( 
 input [REGISTER_WIDTH-1:0] Data_in, 
 input Clk, 
 input resetn, 
 input write, 
 output reg [REGISTER_WIDTH-1:0] Data_out 
 ); 

 reg Secure_mode; 

 always @(posedge Clk or negedge resetn) 

```
   if (~resetn) 
   begin 
  	 Data_out <= REGISTER_DEFAULT; // Register content set to Default at reset 
  	 Secure_mode <= REGISTER_DEFAULT[0]; // Register Secure_mode set at reset 
   end 
   else if (write & ~Secure_mode) 
   begin 
  	 Data_out <= Data_in; 
   end 
 endmodule 
 module register_top 
 ( 
 input Clk, 
 input resetn, 
 input write, 
 input [31:0] Data_in, 
 output reg [31:0] Secure_reg, 
 output reg [31:0] Insecure_reg 
 ); 
 register_example #( 
   .REGISTER_WIDTH (32), 
   .REGISTER_DEFAULT (1224) // Incorrect Default value used bit 0 is 0. 
 ) Insecure_Device_ID_1 ( 
   .Data_in (Data_in), 
   .Data_out (Secure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 ); 
 register_example #(
   .REGISTER_WIDTH (32) // Default not defined 2^32-2 value will be used as default. 
 ) Insecure_Device_ID_2 ( 
   .Data_in (Data_in), 
   .Data_out (Insecure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 ); 
 endmodule

Exemplo de código seguro

Secure Verilog

In the example design, both registers will be software writable since Secure_mode is defined as zero.

Seguro Verilog

register_example #( 

```
   .REGISTER_WIDTH (32), 
   .REGISTER_DEFAULT (1225) // Correct default value set, to enable Secure_mode 
 ) Secure_Device_ID_example ( 
   .Data_in (Data_in), 
   .Data_out (Secure_reg), 
   .Clk (Clk), 
   .resetn (resetn), 
   .write (write) 
 );

What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.

Lista de verificação de prevenção

How to prevent CWE-1221

Architecture and Design During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings.
Implementation The default values of these security sensitive settings need to be defined as part of the design review phase.
Testing Testing phase should use automated tools to test that values are configured per design specifications.

Sinais de deteção

How to detect CWE-1221

SAST High

Executar análise estática (SAST) na base de código à procura do padrão inseguro no fluxo de dados.

DAST Moderate

Executar testes dinâmicos de segurança de aplicações (DAST) contra o endpoint em execução.

Runtime Moderate

Monitorizar os registos em tempo de execução para traços de exceção invulgares, input malformado ou tentativas de contornar a autorização.

Code review Moderate

Revisão de código: sinalizar qualquer novo código que trate input desta superfície sem usar os ajudantes validados do framework.

Correção automática do Plexicus

O Plexicus deteta automaticamente o CWE-1221 e abre um PR de correção em menos de 60 segundos.

O Codex Remedium analisa cada commit, identifica esta fraqueza exata e entrega um pull request pronto para revisão com o patch. Sem tickets. Sem transferências.

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Perguntas frequentes

Frequently asked questions

O que é o CWE-1221?

Qual a gravidade do CWE-1221?

A MITRE não publicou uma classificação de probabilidade de exploração para esta fraqueza. Trate-a como impacto médio até o seu modelo de ameaças provar o contrário.

Que linguagens ou plataformas são afetadas pelo CWE-1221?

MITRE lists the following affected platforms: Verilog, VHDL, Not Technology-Specific.

Como posso prevenir o CWE-1221?

During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings. The default values of these security sensitive settings need to be defined as part of the design review phase.

Como é que o Plexicus deteta e corrige o CWE-1221?

O motor SAST do Plexicus correlaciona a assinatura de fluxo de dados do CWE-1221 em cada commit. Quando é encontrada uma correspondência, o nosso agente Codex Remedium abre um PR de correção com o código corrigido, testes e um resumo de uma linha para o revisor.

Onde posso saber mais sobre o CWE-1221?

A MITRE publica a definição canónica em https://cwe.mitre.org/data/definitions/1221.html. Pode também consultar a documentação da OWASP e do NIST para orientações adjacentes.

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Recursos

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