Executar análise estática (SAST) na base de código à procura do padrão inseguro no fluxo de dados.
CWE-1257 Base Incompleto
Improper Access Control Applied to Mirrored or Aliased Memory Regions
This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to apply consistent read/write permissions across all these…
Definição
What is CWE-1257?
This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to apply consistent read/write permissions across all these addresses. An attacker blocked from accessing a protected memory region might still reach the same data through its unprotected aliased address, bypassing security controls.
Hardware designs often use memory aliasing for legitimate purposes like redundancy, fault tolerance, or simplifying address decoding logic. However, a critical security flaw emerges when the access control logic checks permissions for only one address path and not its aliases. This creates an inconsistent security state where the same physical memory cell has different protection levels depending on which logical address is used to access it.
From a developer or attacker perspective, this inconsistency becomes an exploitable bypass. An untrusted process or agent denied access to a primary address can simply target the alternate, aliased address to read or write protected memory. Furthermore, if an attacker can manipulate system address mapping registers, they might be able to create malicious aliases themselves, fundamentally undermining the hardware's memory isolation guarantees.
Impacto no mundo real
Real-world CVEs caused by CWE-1257
Ainda não há referências CVE públicas associadas a este CWE no catálogo da MITRE.
Como os atacantes a exploram
Trajeto do atacante passo a passo
- 1
Identificar um caminho de código que trata input não confiável sem validação.
- 2
Criar um payload que explora o comportamento inseguro — injeção, traversal, overflow ou abuso de lógica.
- 3
Entregar o payload através de um pedido normal e observar a reação da aplicação.
- 4
Iterar até que a resposta exponha dados, execute código do atacante ou escale privilégios.
Exemplo de código vulnerável
Vulnerable Other
In a System-on-a-Chip (SoC) design the system fabric uses 16 bit addresses. An IP unit (Unit_A) has 4 kilobyte of internal memory which is mapped into a 16 kilobyte address range in the system fabric address map. | | | | System Address | Mapped to | | 0x0000 - 0x3FFF | Unit_A registers : 0x0000 - 0x0FFF | | 0x4000 - 0xFFFF | Other IPs & Memory | To protect the register controls in Unit_A unprivileged software is blocked from accessing addresses between 0x0000 - 0x0FFF. The address decoder of Unit_A masks off the higher order address bits and decodes only the lower 12 bits for computing the offset into the 4 kilobyte internal memory space.
In this design the aliased memory address ranges are these:
0x0000 - 0x0FFF
0x1000 - 0x1FFF
0x2000 - 0x2FFF
0x3000 - 0x3FFF
The same register can be accessed using four different addresses: 0x0000, 0x1000, 0x2000, 0x3000.
The system address filter only blocks access to range 0x0000 - 0x0FFF and does not block access to the aliased addresses in 0x1000 - 0x3FFF range. Thus, untrusted software can leverage the aliased memory addresses to bypass the memory protection. Exemplo de código seguro
Secure Other
In this design the aliased memory addresses (0x1000 - 0x3FFF) could be blocked from all system software access since they are not used by software.
Alternately, the MPU logic can be changed to apply the memory protection policies to the full address range mapped to Unit_A (0x0000 - 0x3FFF). What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Lista de verificação de prevenção
How to prevent CWE-1257
- Architecture and Design / Implementation The checks should be applied for consistency access rights between primary memory regions and any mirrored or aliased memory regions. If different memory protection units (MPU) are protecting the aliased regions, their protected range definitions and policies should be synchronized.
- Architecture and Design / Implementation The controls that allow enabling memory aliases or changing the size of mapped memory regions should only be programmable by trusted software components.
Sinais de deteção
How to detect CWE-1257
Executar testes dinâmicos de segurança de aplicações (DAST) contra o endpoint em execução.
Monitorizar os registos em tempo de execução para traços de exceção invulgares, input malformado ou tentativas de contornar a autorização.
Revisão de código: sinalizar qualquer novo código que trate input desta superfície sem usar os ajudantes validados do framework.
O Plexicus deteta automaticamente o CWE-1257 e abre um PR de correção em menos de 60 segundos.
O Codex Remedium analisa cada commit, identifica esta fraqueza exata e entrega um pull request pronto para revisão com o patch. Sem tickets. Sem transferências.
Perguntas frequentes O que é o CWE-1257?
Qual a gravidade do CWE-1257?
Que linguagens ou plataformas são afetadas pelo CWE-1257?
Como posso prevenir o CWE-1257?
Como é que o Plexicus deteta e corrige o CWE-1257?
Onde posso saber mais sobre o CWE-1257?
Frequently asked questions
O que é o CWE-1257?
This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to apply consistent read/write permissions across all these addresses. An attacker blocked from accessing a protected memory region might still reach the same data through its unprotected aliased address, bypassing security controls.
Qual a gravidade do CWE-1257?
A MITRE não publicou uma classificação de probabilidade de exploração para esta fraqueza. Trate-a como impacto médio até o seu modelo de ameaças provar o contrário.
Que linguagens ou plataformas são afetadas pelo CWE-1257?
MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Memory Hardware, Processor Hardware, Microcontroller Hardware, Network on Chip Hardware, System on Chip.
Como posso prevenir o CWE-1257?
The checks should be applied for consistency access rights between primary memory regions and any mirrored or aliased memory regions. If different memory protection units (MPU) are protecting the aliased regions, their protected range definitions and policies should be synchronized. The controls that allow enabling memory aliases or changing the size of mapped memory regions should only be programmable by trusted software components.
Como é que o Plexicus deteta e corrige o CWE-1257?
O motor SAST do Plexicus correlaciona a assinatura de fluxo de dados do CWE-1257 em cada commit. Quando é encontrada uma correspondência, o nosso agente Codex Remedium abre um PR de correção com o código corrigido, testes e um resumo de uma linha para o revisor.
Onde posso saber mais sobre o CWE-1257?
A MITRE publica a definição canónica em https://cwe.mitre.org/data/definitions/1257.html. Pode também consultar a documentação da OWASP e do NIST para orientações adjacentes.
Fraquezas relacionadas
Weaknesses related to CWE-1257
CWE-284 Pai
Improper Access Control
The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.
CWE-1191 Irmão
On-Chip Debug and Test Interface With Improper Access Control
This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…
CWE-1220 Irmão
Insufficient Granularity of Access Control
This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…
CWE-1224 Irmão
Improper Restriction of Write-Once Bit Fields
This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented,…
CWE-1231 Irmão
Improper Prevention of Lock Bit Modification
This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to…
CWE-1233 Irmão
Security-Sensitive Hardware Controls with Missing Lock Bit Protection
This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to…
CWE-1252 Irmão
CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…
CWE-1259 Irmão
Improper Restriction of Security Token Assignment
This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…
CWE-1260 Irmão
Improper Handling of Overlap Between Protected Memory Ranges
This vulnerability occurs when a system incorrectly allows different memory protection ranges to overlap. This flaw can let attackers…
Pronto quando você estiver
Pare de pagar por desenvolvedor.
Comece a fechar o ciclo.
O Plexicus é o ASPM nativo de IA que verifica, filtra, corrige, pentesta e explica — de forma autónoma. Programadores ilimitados, repos ilimitados, ações de IA de utilização justa. Nível gratuito real, €269/mo anual quando estiver pronto.