Expected Behavior Violation

What is CWE-440?

Trajeto do atacante passo a passo

1. 1

   The provided code is extracted from the Control and Status Register (CSR), csr_regfile, module within the Hack@DAC'21 OpenPiton System-on-Chip (SoC). This module is designed to implement CSR registers in accordance with the RISC-V specification. The mie (machine interrupt enable) register is a 64-bit register [REF-1384], where bits correspond to different interrupt sources. As the name suggests, mie is a machine-level register that determines which interrupts are enabled. Note that in the example below the mie_q and mie_d registers represent the conceptual mie reigster in the RISC-V specification. The mie_d register is the value to be stored in the mie register while the mie_q register holds the current value of the mie register [REF-1385].

2. 2

   The mideleg (machine interrupt delegation) register, also 64-bit wide, enables the delegation of specific interrupt sources from machine privilege mode to lower privilege levels. By setting specific bits in the mideleg register, the handling of certain interrupts can be delegated to lower privilege levels without engaging the machine-level privilege mode. For example, in supervisor mode, the mie register is limited to a specific register called the sie (supervisor interrupt enable) register. If delegated, an interrupt becomes visible in the sip (supervisor interrupt pending) register and can be enabled or blocked using the sie register. If no delegation occurs, the related bits in sip and sie are set to zero.

3. 3

   The sie register value is computed based on the current value of mie register, i.e., mie_q, and the mideleg register.

4. 4

   The above code snippet illustrates an instance of a vulnerable implementation of the sie register update logic, where users can tamper with the mie_d register value through the utval (user trap value) register. This behavior violates the RISC-V specification.

5. 5

   The code shows that the value of utval, among other signals, is used in updating the mie_d value within the sie update logic. While utval is a register accessible to users, it should not influence or compromise the integrity of sie. Through manipulation of the utval register, it becomes feasible to manipulate the sie register's value. This opens the door for potential attacks, as an adversary can gain control over or corrupt the sie value. Consequently, such manipulation empowers an attacker to enable or disable critical supervisor-level interrupts, resulting in various security risks such as privilege escalation or denial-of-service attacks.

How to prevent CWE-440

• Architecture Use safe-by-default frameworks and APIs that prevent the unsafe pattern from being expressible.
• Implementation Validate input at trust boundaries; use allowlists, not denylists.
• Implementation Apply the principle of least privilege to credentials, file paths, and runtime permissions.
• Testing Cover this weakness in CI: SAST rules + targeted unit tests for the data flow.
• Operation Monitor logs for the runtime signals listed in the next section.

Frequently asked questions

Further reading

• MITRE — CWE-440 oficial https://cwe.mitre.org/data/definitions/440.html
• The RISC-V Instruction Set Manual Volume II: Privileged Architecture page 28 https://riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf
• csr_regfile.sv https://github.com/HACK-EVENT/hackatdac21/blob/b9ecdf6068445d76d6bee692d163fededf7a9d9b/piton/design/chip/tile/ariane/src/csr_regfile.sv
• Fix for csr_regfile.sv https://github.com/HACK-EVENT/hackatdac21/blob/2341c625a28d2fb87d370e32c45b68bd711cc43b/piton/design/chip/tile/ariane/src/csr_regfile.sv#L519C4-L522C20