CWE-1234 Base Incomplet

Hardware Internal or Debug Modes Allow Override of Locks

Hardware debug modes or internal states can bypass critical system lock protections, allowing unauthorized changes to device configuration.

Définition

What is CWE-1234?

Hardware debug modes or internal states can bypass critical system lock protections, allowing unauthorized changes to device configuration.
Many hardware systems use a lock bit—often set by trusted firmware like a BIOS or bootloader during startup—to permanently protect crucial configuration registers. Once this lock is engaged, it should prevent any further modification to settings that control system security, such as memory protection units. However, if the hardware design includes special debug modes or internal testing states, these privileged pathways can sometimes override the lock, defeating its primary purpose. This creates a significant vulnerability because an attacker with access to these debug features can alter foundational system configurations after they were supposedly locked down. Developers must ensure that hardware lock mechanisms are truly immutable and that all debug and test modes are thoroughly assessed and disabled before deployment to prevent such overrides.
Impact réel

Real-world CVEs caused by CWE-1234

Aucune référence CVE publique n'est liée à ce CWE dans le catalogue MITRE pour le moment.

Comment les attaquants l'exploitent

Parcours de l'attaquant étape par étape

  1. 1

    For example, consider the example Locked_override_register example. This register module supports a lock mode that blocks any writes after lock is set to 1. However, it also allows override of the lock protection when scan_mode or debug_unlocked modes are active.

  2. 2

    If either the scan_mode or the debug_unlocked modes can be triggered by software, then the lock protection may be bypassed.

  3. 3

    The following example code [REF-1375] is taken from the register lock security peripheral of the HACK@DAC'21 buggy OpenPiton SoC. It demonstrates how to lock read or write access to security-critical hardware registers (e.g., crypto keys, system integrity code, etc.). The configuration to lock all the sensitive registers in the SoC is managed through the reglk_mem registers. These reglk_mem registers are reset when the hardware powers up and configured during boot up. Malicious users, even with kernel-level software privilege, do not get access to the sensitive contents that are locked down. Hence, the security of the entire system can potentially be compromised if the register lock configurations are corrupted or if the register locks are disabled.

  4. 4

    The example code [REF-1375] illustrates an instance of a vulnerable implementation of register locks in the SoC. In this flawed implementation [REF-1375], the reglk_mem registers are also being reset when the system enters debug mode (indicated by the jtag_unlock signal). Consequently, users can simply put the processor in debug mode to access sensitive contents that are supposed to be protected by the register lock feature.

  5. 5

    This can be mitigated by excluding debug mode signals from the reset logic of security-critical register locks as demonstrated in the following code snippet [REF-1376].

Exemple de code vulnérable

Vulnerable Verilog

For example, consider the example Locked_override_register example. This register module supports a lock mode that blocks any writes after lock is set to 1. However, it also allows override of the lock protection when scan_mode or debug_unlocked modes are active.

Vulnérable Verilog 
module Locked_register_example
 (
 input [15:0] Data_in,
 input Clk,
 input resetn,
 input write,
 input Lock,
 input scan_mode,
 input debug_unlocked,
 output reg [15:0] Data_out
 );

 reg lock_status;

 always @(posedge Clk or negedge resetn)

```
   if (~resetn) // Register is reset resetn
   begin
  	 lock_status <= 1'b0;
   end
   else if (Lock)
   begin
  	 lock_status <= 1'b1;
   end
   else if (~Lock)
   begin
  	 lock_status <= lock_status
   end
 always @(posedge Clk or negedge resetn)
   if (~resetn) // Register is reset resetn
   begin
  	 Data_out <= 16'h0000;
   end
   else if (write & (~lock_status | scan_mode | debug_unlocked) ) // Register protected by Lock bit input, overrides supported for scan_mode & debug_unlocked
   begin
  	 Data_out <= Data_in;
   end
   else if (~write)
   begin
  	 Data_out <= Data_out;
   end
 endmodule
Exemple de code sécurisé

Secure code

If either the scan_mode or the debug_unlocked modes can be triggered by software, then the lock protection may be bypassed.

Sécurisé 
Either remove the debug and scan mode overrides or protect enabling of these modes so that only trusted and authorized users may enable these modes.
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Liste de contrôle de prévention

How to prevent CWE-1234

  • Architecture and Design / Implementation / Testing - Security Lock bit protections should be reviewed for any bypass/override modes supported. - Any supported override modes either should be removed or protected using authenticated debug modes. - Security lock programming flow and lock properties should be tested in pre-silicon and post-silicon testing.
Signaux de détection

How to detect CWE-1234

SAST High

Exécuter une analyse statique (SAST) sur le code source à la recherche du motif non sécurisé dans le flux de données.

DAST Moderate

Exécuter des tests de sécurité applicative dynamique (DAST) contre le point de terminaison en ligne.

Runtime Moderate

Surveiller les journaux runtime pour détecter des traces d'exception inhabituelles, des entrées malformées ou des tentatives de contournement d'autorisation.

Code review Moderate

Revue de code : signaler tout nouveau code qui traite les entrées de cette surface sans utiliser les helpers du framework validés.

Correction automatique Plexicus

Plexicus détecte automatiquement CWE-1234 et ouvre une PR de correction en moins de 60 secondes.

Codex Remedium analyse chaque commit, identifie cette faiblesse précise et livre une pull request prête à être relue avec le correctif. Pas de tickets. Pas de transferts.

Obtenir une démo Essayer Plexicus gratuitement
Questions fréquentes

Frequently asked questions

Qu'est-ce que CWE-1234 ?

Hardware debug modes or internal states can bypass critical system lock protections, allowing unauthorized changes to device configuration.

Quelle est la gravité de CWE-1234 ?

MITRE n'a pas publié de note de probabilité d'exploitation pour cette faiblesse. Traitez-la comme un impact moyen jusqu'à ce que votre modèle de menace prouve le contraire.

Quels langages ou plateformes sont affectés par CWE-1234 ?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Not Technology-Specific.

Comment puis-je prévenir CWE-1234 ?

- Security Lock bit protections should be reviewed for any bypass/override modes supported. - Any supported override modes either should be removed or protected using authenticated debug modes. - Security lock programming flow and lock properties should be tested in pre-silicon and post-silicon testing.

Comment Plexicus détecte et corrige CWE-1234 ?

Le moteur SAST de Plexicus reconnaît la signature de flux de données de CWE-1234 à chaque commit. Lorsqu'une correspondance est trouvée, notre agent Codex Remedium ouvre une PR de correction avec le code corrigé, les tests et un résumé d'une ligne pour le relecteur.

Où puis-je en savoir plus sur CWE-1234 ?

MITRE publie la définition canonique à https://cwe.mitre.org/data/definitions/1234.html. Vous pouvez également consulter la documentation OWASP et NIST pour des conseils adjacents.

Faiblesses associées

Weaknesses related to CWE-1234

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CWE-1233 Frère

Security-Sensitive Hardware Controls with Missing Lock Bit Protection

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CWE-412 Frère

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CWE-413 Frère

Improper Resource Locking

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CWE-414 Frère

Missing Lock Check

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CWE-609 Frère

Double-Checked Locking

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CWE-764 Frère

Multiple Locks of a Critical Resource

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CWE-765 Frère

Multiple Unlocks of a Critical Resource

This vulnerability occurs when a critical resource, like a lock or semaphore, is unlocked more times than it was locked, putting the…

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