Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.
Incorrect Chaining or Granularity of Debug Components
This vulnerability occurs when hardware debug components, such as test ports and scan chains, are incorrectly connected or organized within a chip's design. This misconfiguration can create…
What is CWE-1296?
Real-world CVEs caused by CWE-1296
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Incorrect access control in RDP Level 1 on STMicroelectronics STM32F0 series devices allows physically present attackers to extract the device's protected firmware via a special sequence of Serial Wire Debug (SWD) commands because there is a race condition between full initialization of the SWD interface and the setup of flash protection.
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There is an improper authorization vulnerability in several smartphones. The system has a logic-judging error, and, under certain scenarios, a successful exploit could allow the attacker to switch to third desktop after a series of operations in ADB mode. (Vulnerability ID: HWPSIRT-2019-10114).
Trajeto do atacante passo a passo
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The following example shows how an attacker can take advantage of incorrect chaining or missing granularity of debug components.
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In a System-on-Chip (SoC), the user might be able to access the SoC-level TAP with a certain level of authorization. However, this access should not also grant access to all of the internal TAPs (e.g., Core). Separately, if any of the internal TAPs is also stitched to the TAP chain when it should not be because of a logic error, then an attacker can access the internal TAPs as well and execute commands there.
- 3
As a related example, suppose there is a hierarchy of TAPs (TAP_A is connected to TAP_B and TAP_C, then TAP_B is connected to TAP_D and TAP_E, then TAP_C is connected to TAP_F and TAP_G, etc.). Architecture mandates that the user have one set of credentials for just accessing TAP_A, another set of credentials for accessing TAP_B and TAP_C, etc. However, if, during implementation, the designer mistakenly implements a daisy-chained TAP where all the TAPs are connected in a single TAP chain without the hierarchical structure, the correct granularity of debug components is not implemented and the attacker can gain unauthorized access.
Vulnerable pseudo
A MITRE não publicou um exemplo de código para este CWE. O padrão abaixo é ilustrativo — consulte os Recursos para referências canónicas.
// Example pattern — see MITRE for the canonical references.
function handleRequest(input) {
// Untrusted input flows directly into the sensitive sink.
return executeUnsafe(input);
} Secure pseudo
// Validate, sanitize, or use a safe API before reaching the sink.
function handleRequest(input) {
const safe = validateAndEscape(input);
return executeWithGuards(safe);
} How to prevent CWE-1296
- Implementation Ensure that debug components are properly chained and their granularity is maintained at different authentication levels.
How to detect CWE-1296
Appropriate Post-Si tests should be carried out at various authorization levels to ensure that debug components are properly chained and accessible only to users with appropriate credentials.
O Plexicus deteta automaticamente o CWE-1296 e abre um PR de correção em menos de 60 segundos.
O Codex Remedium analisa cada commit, identifica esta fraqueza exata e entrega um pull request pronto para revisão com o patch. Sem tickets. Sem transferências.
Frequently asked questions
O que é o CWE-1296?
This vulnerability occurs when hardware debug components, such as test ports and scan chains, are incorrectly connected or organized within a chip's design. This misconfiguration can create unintended access paths, potentially exposing sensitive internal data or functions.
Qual a gravidade do CWE-1296?
A MITRE não publicou uma classificação de probabilidade de exploração para esta fraqueza. Trate-a como impacto médio até o seu modelo de ameaças provar o contrário.
Que linguagens ou plataformas são afetadas pelo CWE-1296?
MITRE lists the following affected platforms: Verilog, VHDL, Not OS-Specific, Not Architecture-Specific, Processor Hardware, Not Technology-Specific.
Como posso prevenir o CWE-1296?
Ensure that debug components are properly chained and their granularity is maintained at different authentication levels.
Como é que o Plexicus deteta e corrige o CWE-1296?
O motor SAST do Plexicus correlaciona a assinatura de fluxo de dados do CWE-1296 em cada commit. Quando é encontrada uma correspondência, o nosso agente Codex Remedium abre um PR de correção com o código corrigido, testes e um resumo de uma linha para o revisor.
Onde posso saber mais sobre o CWE-1296?
A MITRE publica a definição canónica em https://cwe.mitre.org/data/definitions/1296.html. Pode também consultar a documentação da OWASP e do NIST para orientações adjacentes.
Weaknesses related to CWE-1296
Improper Access Control
The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.
On-Chip Debug and Test Interface With Improper Access Control
This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…
Insufficient Granularity of Access Control
This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…
Improper Restriction of Write-Once Bit Fields
This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented,…
Improper Prevention of Lock Bit Modification
This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to…
Security-Sensitive Hardware Controls with Missing Lock Bit Protection
This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to…
CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…
Improper Access Control Applied to Mirrored or Aliased Memory Regions
This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to…
Improper Restriction of Security Token Assignment
This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…
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