CWE-1244 Base Stable

Internal Asset Exposed to Unsafe Debug Access Level or State

This vulnerability occurs when a system's debug or test interface supports multiple access levels, but an internal asset is incorrectly assigned a permissive debug access level. This mistake allows…

Définition

What is CWE-1244?

This vulnerability occurs when a system's debug or test interface supports multiple access levels, but an internal asset is incorrectly assigned a permissive debug access level. This mistake allows untrusted debug agents to access sensitive internal assets they should not be able to reach.
Modern debug and test interfaces often implement tiered access control, where different internal components become accessible based on the currently authorized debug level or the system's operational state. This authorization isn't just about passwords; it can also depend on the boot stage or system mode. For instance, full debug access might only be permitted immediately after a reset to prevent leakage of data from a previous session. If this protection fails and an internal asset is exposed at an unsafe debug level during a specific state or boot phase, an attacker with debugger access can exploit this to read sensitive information. The core failure is the system's inability to correctly map and enforce the appropriate debug access level for each asset as the system state changes, creating a window of unintended exposure.
Impact réel

Real-world CVEs caused by CWE-1244

  • CVE-2019-18827

    After ROM code execution, JTAG access is disabled. But before the ROM code is executed, JTAG access is possible, allowing a user full system access. This allows a user to modify the boot flow and successfully bypass the secure-boot process.

Comment les attaquants l'exploitent

Parcours de l'attaquant étape par étape

  1. 1

    The JTAG interface is used to perform debugging and provide CPU core access for developers. JTAG-access protection is implemented as part of the JTAG_SHIELD bit in the hw_digctl_ctrl register. This register has no default value at power up and is set only after the system boots from ROM and control is transferred to the user software.

  2. 2

    This means that since the end user has access to JTAG at system reset and during ROM code execution before control is transferred to user software, a JTAG user can modify the boot flow and subsequently disclose all CPU information, including data-encryption keys.

  3. 3

    The example code below is taken from the CVA6 processor core of the HACK@DAC'21 buggy OpenPiton SoC. Debug access allows users to access internal hardware registers that are otherwise not exposed for user access or restricted access through access control protocols. Hence, requests to enter debug mode are checked and authorized only if the processor has sufficient privileges. In addition, debug accesses are also locked behind password checkers. Thus, the processor enters debug mode only when the privilege level requirement is met, and the correct debug password is provided.

  4. 4

    The following code [REF-1377] illustrates an instance of a vulnerable implementation of debug mode. The core correctly checks if the debug requests have sufficient privileges and enables the debug_mode_d and debug_mode_q signals. It also correctly checks for debug password and enables umode_i signal.

  5. 5

    However, it grants debug access and changes the privilege level, priv_lvl_o, even when one of the two checks is satisfied and the other is not. Because of this, debug access can be granted by simply requesting with sufficient privileges (i.e., debug_mode_q is enabled) and failing the password check (i.e., umode_i is disabled). This allows an attacker to bypass the debug password checking and gain debug access to the core, compromising the security of the processor.

Exemple de code vulnérable

Vulnerable Other

The JTAG interface is used to perform debugging and provide CPU core access for developers. JTAG-access protection is implemented as part of the JTAG_SHIELD bit in the hw_digctl_ctrl register. This register has no default value at power up and is set only after the system boots from ROM and control is transferred to the user software.

Vulnérable Other 
|  | 
|
| 1 bit | 0x0 = JTAG debugger is enabled (default)  |
| JTAG_SHIELD | 0x1 = JTAG debugger is disabled  |
Exemple de code sécurisé

Secure Verilog

A fix to this issue is to only change the privilege level of the processor when both checks are satisfied, i.e., the request has enough privileges (i.e., debug_mode_q is enabled) and the password checking is successful (i.e., umode_i is enabled) [REF-1378].

Sécurisé Verilog 
module csr_regfile #(
 ...

```
   // check that we actually want to enter debug depending on the privilege level we are currently in
   unique case (priv_lvl_o)
  	 riscv::PRIV_LVL_M: begin
  		 debug_mode_d = dcsr_q.ebreakm;
 ...
  	 riscv::PRIV_LVL_U: begin
  		 debug_mode_d = dcsr_q.ebreaku;
 ...
   assign priv_lvl_o = 
```
(debug_mode_q && umode_i) ? riscv::PRIV_LVL_M : priv_lvl_q;** 
   ...

```
   debug_mode_q <= debug_mode_d;
 ...
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Liste de contrôle de prévention

How to prevent CWE-1244

  • Architecture and Design / Implementation For security-sensitive assets accessible over debug/test interfaces, only allow trusted agents.
  • Architecture and Design Apply blinding [REF-1219] or masking techniques in strategic areas.
  • Implementation Add shielding or tamper-resistant protections to the device, which increases the difficulty and cost for accessing debug/test interfaces.
Signaux de détection

How to detect CWE-1244

Manual Analysis Moderate

Check 2 devices for their passcode to authenticate access to JTAG/debugging ports. If the passcodes are missing or the same, update the design to fix and retest. Check communications over JTAG/debugging ports for encryption. If the communications are not encrypted, fix the design and retest.

Correction automatique Plexicus

Plexicus détecte automatiquement CWE-1244 et ouvre une PR de correction en moins de 60 secondes.

Codex Remedium analyse chaque commit, identifie cette faiblesse précise et livre une pull request prête à être relue avec le correctif. Pas de tickets. Pas de transferts.

Obtenir une démo Essayer Plexicus gratuitement
Questions fréquentes

Frequently asked questions

Qu'est-ce que CWE-1244 ?

This vulnerability occurs when a system's debug or test interface supports multiple access levels, but an internal asset is incorrectly assigned a permissive debug access level. This mistake allows untrusted debug agents to access sensitive internal assets they should not be able to reach.

Quelle est la gravité de CWE-1244 ?

MITRE n'a pas publié de note de probabilité d'exploitation pour cette faiblesse. Traitez-la comme un impact moyen jusqu'à ce que votre modèle de menace prouve le contraire.

Quels langages ou plateformes sont affectés par CWE-1244 ?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, System on Chip.

Comment puis-je prévenir CWE-1244 ?

For security-sensitive assets accessible over debug/test interfaces, only allow trusted agents. Apply blinding [REF-1219] or masking techniques in strategic areas.

Comment Plexicus détecte et corrige CWE-1244 ?

Le moteur SAST de Plexicus reconnaît la signature de flux de données de CWE-1244 à chaque commit. Lorsqu'une correspondance est trouvée, notre agent Codex Remedium ouvre une PR de correction avec le code corrigé, les tests et un résumé d'une ligne pour le relecteur.

Où puis-je en savoir plus sur CWE-1244 ?

MITRE publie la définition canonique à https://cwe.mitre.org/data/definitions/1244.html. Vous pouvez également consulter la documentation OWASP et NIST pour des conseils adjacents.

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