CWE-1276 Base Incompleto

Hardware Child Block Incorrectly Connected to Parent System

This vulnerability occurs when a hardware component (IP block) is wired incorrectly to the main system, creating hidden security flaws even if basic functions appear to work.

Definição

What is CWE-1276?

This vulnerability occurs when a hardware component (IP block) is wired incorrectly to the main system, creating hidden security flaws even if basic functions appear to work.
For a system-on-chip (SoC) to operate securely, its internal hardware blocks must communicate with the parent system using the correct control and data signals. An incorrect connection—like linking a reset pin to the wrong system controller—can bypass critical security boundaries. While the device might still boot and run, this miswiring opens a backdoor that attackers can exploit to tamper with sensitive data or operations. Consider a block designed to only clear its data during a full system power cycle. If its reset line is mistakenly connected to a software-controlled debug reset, a privileged process or an attacker gaining software access could trigger an unauthorized reset. This violates the hardware's data integrity guarantees, potentially leaking secrets or corrupting secure state, all while the system seems to function normally from a user's perspective.
Impacto no mundo real

Real-world CVEs caused by CWE-1276

Ainda não há referências CVE públicas associadas a este CWE no catálogo da MITRE.

Como os atacantes a exploram

Trajeto do atacante passo a passo

  1. 1

    Many SoCs use hardware to partition system resources between trusted and un-trusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.

  2. 2

    In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded.

  3. 3

    Here is a code snippet from the Ariane core module in the HACK@DAC'21 Openpiton SoC [REF-1362]. To ensure full functional correctness, developers connect the ports with names. However, in some cases developers forget to connect some of these ports to the desired signals in the parent module. These mistakes by developers can lead to incorrect functional behavior or, in some cases, introduce security vulnerabilities.

  4. 4

    In the above example from HACK@DAC'21, since interrupt signals are not properly connected, the CSR module will fail to send notifications in the event of interrupts. Consequently, critical information in CSR registers that should be flushed or modified in response to an interrupt won't be updated. These vulnerabilities can potentially result in information leakage across various privilege levels.

  5. 5

    To address the aforementioned vulnerability, developers must follow a two-step approach. First, they should ensure that all module signals are properly connected. This can often be facilitated using automated tools, and many simulators and sanitizer tools issue warnings when a signal remains unconnected or floats. Second, it is imperative to validate that the signals connected to a module align with the specifications. In the provided example, the developer should establish the correct connection of interrupt signals from the parent module (Ariane core) to the child module (csr_regfile) [REF-1363].

Exemplo de código vulnerável

Vulnerable Verilog

Many SoCs use hardware to partition system resources between trusted and un-trusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.

Vulnerável Verilog 
// IP definition
 module tz_peripheral(clk, reset, data_in, data_in_security_level, ...);

```
   input clk, reset;
   input [31:0] data_in;
   input data_in_security_level;
   ...
 endmodule
 // Instantiation of IP in a parent system
 module soc(...)
   ...
   tz_peripheral u_tz_peripheral(
  	 .clk(clk),
  	 .rst(rst),
  	 .data_in(rdata),
  	 //Copy-and-paste error or typo grounds data_in_security_level (in this example 0=secure, 1=non-secure) effectively promoting all data to "secure")
  	 .data_in_security_level(1'b0),
   );
   ...
 endmodule
Exemplo de código seguro

Secure Verilog

In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded.

Seguro Verilog 
// Instantiation of IP in a parent system
 module soc(...)

```
   ...
   tz_peripheral u_tz_peripheral(
  	 .clk(clk),
  	 .rst(rst),
  	 .data_in(rdata),
  	 // This port is no longer grounded, but instead driven by the appropriate signal
  	 .data_in_security_level(rdata_security_level),
   );
   ...
 endmodule
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Lista de verificação de prevenção

How to prevent CWE-1276

  • Testing System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks.
Sinais de deteção

How to detect CWE-1276

SAST High

Executar análise estática (SAST) na base de código à procura do padrão inseguro no fluxo de dados.

DAST Moderate

Executar testes dinâmicos de segurança de aplicações (DAST) contra o endpoint em execução.

Runtime Moderate

Monitorizar os registos em tempo de execução para traços de exceção invulgares, input malformado ou tentativas de contornar a autorização.

Code review Moderate

Revisão de código: sinalizar qualquer novo código que trate input desta superfície sem usar os ajudantes validados do framework.

Correção automática do Plexicus

O Plexicus deteta automaticamente o CWE-1276 e abre um PR de correção em menos de 60 segundos.

O Codex Remedium analisa cada commit, identifica esta fraqueza exata e entrega um pull request pronto para revisão com o patch. Sem tickets. Sem transferências.

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Perguntas frequentes

Frequently asked questions

O que é o CWE-1276?

This vulnerability occurs when a hardware component (IP block) is wired incorrectly to the main system, creating hidden security flaws even if basic functions appear to work.

Qual a gravidade do CWE-1276?

A MITRE não publicou uma classificação de probabilidade de exploração para esta fraqueza. Trate-a como impacto médio até o seu modelo de ameaças provar o contrário.

Que linguagens ou plataformas são afetadas pelo CWE-1276?

MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Not Technology-Specific.

Como posso prevenir o CWE-1276?

System-level verification may be used to ensure that components are correctly connected and that design security requirements are not violated due to interactions between various IP blocks.

Como é que o Plexicus deteta e corrige o CWE-1276?

O motor SAST do Plexicus correlaciona a assinatura de fluxo de dados do CWE-1276 em cada commit. Quando é encontrada uma correspondência, o nosso agente Codex Remedium abre um PR de correção com o código corrigido, testes e um resumo de uma linha para o revisor.

Onde posso saber mais sobre o CWE-1276?

A MITRE publica a definição canónica em https://cwe.mitre.org/data/definitions/1276.html. Pode também consultar a documentação da OWASP e do NIST para orientações adjacentes.

Fraquezas relacionadas

Weaknesses related to CWE-1276

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Recursos

Further reading

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