Set the lock bit. Attempt to modify the information protected by the lock bit. If the information is changed, implement a design fix. Retest. Also, attempt to indirectly clear the lock bit or bypass it.
Security-Sensitive Hardware Controls with Missing Lock Bit Protection
This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to prevent writes to all registers that can alter the protected…
What is CWE-1233?
Real-world CVEs caused by CWE-1233
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Certain servers leave a write protection lock bit unset after boot, potentially allowing modification of parts of flash memory.
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Chain: chipset has a race condition (CWE-362) between when an interrupt handler detects an attempt to write-enable the BIOS (in violation of the lock bit), and when the handler resets the write-enable bit back to 0, allowing attackers to issue BIOS writes during the timing window [REF-1237].
Ruta del atacante paso a paso
- 1
Identifica una ruta de código que maneje entrada no confiable sin validación.
- 2
Crea un payload que ejercite el comportamiento inseguro — inyección, traversal, overflow o abuso de lógica.
- 3
Envía el payload a través de una solicitud normal y observa la reacción de la aplicación.
- 4
Itera hasta que la respuesta filtre datos, ejecute código del atacante o escale privilegios.
Vulnerable Other
Consider the example design below for a digital thermal sensor that detects overheating of the silicon and triggers system shutdown. The system critical temperature limit (CRITICAL_TEMP_LIMIT) and thermal sensor calibration (TEMP_SENSOR_CALIB) data have to be programmed by the firmware.
| Register | Field description |
| --- | --- |
| CRITICAL_TEMP_LIMIT | [31:8] Reserved field; Read only; Default 0 [7:0] Critical temp 0-255 Centigrade; Read-write-lock; Default 125 |
| TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. A slope value used to map sensor reading to a degree Centigrade. Read-write; Default 25 |
| TEMP_SENSOR_LOCK | [31:1] Reserved field; Read only; Default 0 [0] Lock bit, locks CRITICAL_TEMP_LIMIT register; Write-1-once; Default 0 |
| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on a critical temperature detection; Read-write; Default 0 |
| CURRENT_TEMP | [31:8] Reserved field; Read only; Default 0 [7:0] Current Temp 0-255 Centigrade; Read-only; Default 0 | Secure Other
In this example note that only the CRITICAL_TEMP_LIMIT register is protected by the TEMP_SENSOR_LOCK bit, while the security design intent is to protect any modification of the critical temperature detection and response. The response of the system, if the system heats to a critical temperature, is controlled by TEMP_HW_SHUTDOWN bit [1], which is not lockable. Also, the TEMP_SENSOR_CALIB register is not protected by the lock bit. By modifying the temperature sensor calibration, the conversion of the sensor data to a degree centigrade can be changed, such that the current temperature will never be detected to exceed critical temperature value programmed by the protected lock. Similarly, by modifying the TEMP_HW_SHUTDOWN.Enable bit, the system response detection of the current temperature exceeding critical temperature can be disabled.
Change TEMP_HW_SHUTDOWN and TEMP_SENSOR_CALIB controls to be locked by TEMP_SENSOR_LOCK.
| |
|
| TEMP_SENSOR_CALIB | [31:0] Thermal sensor calibration data. A slope value used to map sensor reading to a degree Centigrade. Read-write-Lock; Default 25; Locked by TEMP_SENSOR_LOCK bit[0] |
| TEMP_HW_SHUTDOWN | [31:2] Reserved field; Read only; Default 0 [1] Enable hardware shutdown on critical temperature detection; Read-write-Lock; Default 0; Locked by TEMP_SENSOR_LOCK bit[0] | How to prevent CWE-1233
- Architecture and Design / Implementation / Testing - Security lock bit protections must be reviewed for design inconsistency and common weaknesses. - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.
How to detect CWE-1233
Plexicus detecta automáticamente CWE-1233 y abre un PR de corrección en menos de 60 segundos.
Codex Remedium escanea cada commit, identifica esta debilidad concreta y entrega un pull request listo para revisión con el parche. Sin tickets. Sin traspasos.
Frequently asked questions
¿Qué es CWE-1233?
This vulnerability occurs when a hardware device uses a lock bit to protect critical configuration registers, but the lock fails to prevent writes to all registers that can alter the protected system settings. Essentially, the security mechanism is incomplete, allowing software to bypass it and modify sensitive hardware configurations.
¿Qué gravedad tiene CWE-1233?
MITRE no ha publicado una calificación de probabilidad de explotación para esta debilidad. Trátala como de impacto medio hasta que tu modelo de amenazas demuestre lo contrario.
¿Qué lenguajes o plataformas se ven afectados por CWE-1233?
MITRE lists the following affected platforms: Not OS-Specific, Not Architecture-Specific, Not Technology-Specific.
¿Cómo puedo prevenir CWE-1233?
- Security lock bit protections must be reviewed for design inconsistency and common weaknesses. - Security lock programming flow and lock properties must be tested in pre-silicon and post-silicon testing.
¿Cómo detecta y corrige Plexicus CWE-1233?
El motor SAST de Plexicus detecta la firma de flujo de datos para CWE-1233 en cada commit. Cuando hay coincidencia, nuestro agente Codex Remedium abre un PR de corrección con el código corregido, las pruebas y un resumen de una línea para el revisor.
¿Dónde puedo aprender más sobre CWE-1233?
MITRE publica la definición canónica en https://cwe.mitre.org/data/definitions/1233.html. También puedes consultar la documentación de OWASP y NIST para guías relacionadas.
Weaknesses related to CWE-1233
Improper Access Control
The software fails to properly limit who can access a resource, allowing unauthorized users or systems to interact with it.
On-Chip Debug and Test Interface With Improper Access Control
This vulnerability occurs when a hardware chip's debug or test interface (like JTAG) lacks proper access controls. Without correct…
Insufficient Granularity of Access Control
This vulnerability occurs when a system's access controls are too broad, allowing unauthorized users or processes to read or modify…
Improper Restriction of Write-Once Bit Fields
This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented,…
Improper Prevention of Lock Bit Modification
This vulnerability occurs when hardware or firmware uses a lock bit to protect critical system registers or memory regions, but fails to…
CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations
This vulnerability occurs when a CPU's hardware is not set up to enforce a strict separation between writing data to memory and executing…
Improper Access Control Applied to Mirrored or Aliased Memory Regions
This vulnerability occurs when a hardware design maps the same physical memory to multiple addresses (aliasing or mirroring) but fails to…
Improper Restriction of Security Token Assignment
This vulnerability occurs when a System-on-a-Chip (SoC) fails to properly secure its Security Token mechanism. These tokens control which…
Improper Handling of Overlap Between Protected Memory Ranges
This vulnerability occurs when a system incorrectly allows different memory protection ranges to overlap. This flaw can let attackers…
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