CWE-1224 Base Incompleto

Improper Restriction of Write-Once Bit Fields

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

Definición

What is CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.
Hardware designs use special write-once or 'sticky' bit fields in control registers to lock critical settings. These are intended to be configured only once—typically during initial boot by trusted firmware—and then become permanently read-only. This mechanism is a fundamental security feature that prevents runtime software or malware from altering secure hardware configurations, such as memory protection or debug access controls. When this restriction fails, software can repeatedly overwrite these bits. A common implementation flaw is creating 'write-1-once' logic instead of true 'write-once' protection. In this flawed scenario, a bit might only become locked after being set to '1,' leaving it vulnerable if set to '0' first or allowing toggling between values. This exposes the hardware to privilege escalation, system compromise, or bypass of critical security boundaries.
Impacto en el mundo real

Real-world CVEs caused by CWE-1224

Todavía no hay CVEs públicos enlazados a esta CWE en el catálogo de MITRE.

Cómo lo explotan los atacantes

Ruta del atacante paso a paso

  1. 1

    Identifica una ruta de código que maneje entrada no confiable sin validación.

  2. 2

    Crea un payload que ejercite el comportamiento inseguro — inyección, traversal, overflow o abuso de lógica.

  3. 3

    Envía el payload a través de una solicitud normal y observa la reacción de la aplicación.

  4. 4

    Itera hasta que la respuesta filtre datos, ejecute código del atacante o escale privilegios.

Ejemplo de código vulnerable

Vulnerable Verilog

Consider the example design module system verilog code shown below. register_write_once_example module is an example of register that has a write-once field defined. Bit 0 field captures the write_once_status value. This implementation can be for a register that is defined by specification to be a write-once register, since the write_once_status field gets written by input data bit 0 on first write.

Vulnerable Verilog 
module register_write_once_example
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn,
 input write,
 output reg [15:0] Data_out 
 );

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn)

```
   if (~ip_resetn)
   begin
  	 Data_out <= 16'h0000;
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status)
   begin
  	 Data_out <= Data_in & 16'hFFFE;
  	 Write_once_status <= Data_in[0]; // Input bit 0 sets Write_once_status
   end
   else if (~write)
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule
Ejemplo de código seguro

Secure Verilog

The above example only locks further writes if write_once_status bit is written to one. So it acts as write_1-Once instead of the write-once attribute.

Seguro Verilog 
module register_write_once_example 
 ( 
 input [15:0] Data_in, 
 input Clk, 
 input ip_resetn, 
 input global_resetn, 
 input write, 
 output reg [15:0] Data_out 
 ); 

 reg Write_once_status; 

 always @(posedge Clk or negedge ip_resetn) 

```
   if (~ip_resetn) 
   begin 
  	 Data_out <= 16'h0000; 
  	 Write_once_status <= 1'b0; 
   end 
   else if (write & ~Write_once_status) 
   begin 
  	 Data_out <= Data_in & 16'hFFFE; 
  	 Write_once_status <= 1'b1; // Write once status set on first write, independent of input 
   end 
   else if (~write) 
   begin 
  	 Data_out[15:1] <= Data_out[15:1]; 
  	 Data_out[0] <= Write_once_status; 
   end 
 endmodule
What changed: the unsafe sink is replaced (or the input is validated/escaped) so the same payload no longer triggers the weakness.
Lista de prevención

How to prevent CWE-1224

  • Architecture and Design During hardware design all register write-once or sticky fields must be evaluated for proper configuration.
  • Testing The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.
Señales de detección

How to detect CWE-1224

SAST High

Ejecuta análisis estático (SAST) sobre el código buscando el patrón inseguro en el flujo de datos.

DAST Moderate

Ejecuta pruebas dinámicas de seguridad de aplicaciones (DAST) contra el endpoint en vivo.

Runtime Moderate

Vigila los logs en tiempo de ejecución para detectar trazas de excepción inusuales, entradas malformadas o intentos de bypass de autorización.

Code review Moderate

Revisión de código: marca cualquier código nuevo que maneje entrada desde esta superficie sin usar los helpers validados del framework.

Auto-corrección de Plexicus

Plexicus detecta automáticamente CWE-1224 y abre un PR de corrección en menos de 60 segundos.

Codex Remedium escanea cada commit, identifica esta debilidad concreta y entrega un pull request listo para revisión con el parche. Sin tickets. Sin traspasos.

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Preguntas frecuentes

Frequently asked questions

¿Qué es CWE-1224?

This vulnerability occurs when hardware write-once protection mechanisms, often called 'sticky bits,' are incorrectly implemented, allowing software to reprogram them multiple times.

¿Qué gravedad tiene CWE-1224?

MITRE no ha publicado una calificación de probabilidad de explotación para esta debilidad. Trátala como de impacto medio hasta que tu modelo de amenazas demuestre lo contrario.

¿Qué lenguajes o plataformas se ven afectados por CWE-1224?

MITRE lists the following affected platforms: Verilog, VHDL, System on Chip.

¿Cómo puedo prevenir CWE-1224?

During hardware design all register write-once or sticky fields must be evaluated for proper configuration. The testing phase should use automated tools to test that values are not reprogrammable and that write-once fields lock on writing zeros.

¿Cómo detecta y corrige Plexicus CWE-1224?

El motor SAST de Plexicus detecta la firma de flujo de datos para CWE-1224 en cada commit. Cuando hay coincidencia, nuestro agente Codex Remedium abre un PR de corrección con el código corregido, las pruebas y un resumen de una línea para el revisor.

¿Dónde puedo aprender más sobre CWE-1224?

MITRE publica la definición canónica en https://cwe.mitre.org/data/definitions/1224.html. También puedes consultar la documentación de OWASP y NIST para guías relacionadas.

Debilidades relacionadas

Weaknesses related to CWE-1224

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CWE-1231 Hermano

Improper Prevention of Lock Bit Modification

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CWE-1233 Hermano

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CWE-1252 Hermano

CPU Hardware Not Configured to Support Exclusivity of Write and Execute Operations

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CWE-1257 Hermano

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CWE-1259 Hermano

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CWE-1260 Hermano

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Recursos

Further reading

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